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FUJITSU SEMICONDUCTOR DATA SHEET
FME-MB96350 rev 7
16-bit Proprietary Microcontroller
CMOS
F2MC-16FX MB96350 Series
MB96F353/F355 MB96F356
DESCRIPTION
MB96350 series is based on Fujitsu's advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed.
Note: F2MC is the abbreviation of Fujitsu Flexible Microcontroller
For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development.
http://edevice.fujitsu.com/micom/en-support/
Copyright(c)2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2010.6
MB96350 Series
FEATURES
Feature Technology * 0.18m CMOS * F2MC-16FX CPU * Up to 56 MHz internal, 17.8 ns instruction cycle time CPU * Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) * 8-byte instruction execution queue * Signed multiply (16-bit x 16-bit) and divide (32-bit/16-bit) instructions available * On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop) * 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using ceramic resonator depends on Q-factor). * Up to 56 MHz external clock * 32-100 kHz subsystem quartz clock System clock * 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection, watchdog * Clock source selectable from main- and subclock oscillator (part number suffix "W") and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals. * Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode) * Clock modulator On-chip voltage regula- * Internal voltage regulator supports reduced internal MCU voltage, offering low EMI tor and low power consumption figures Low voltage reset Code Security Memory Patch Function DMA Interrupts * Reset is generated when supply voltage is below minimum. * Protects ROM content from unintended read-out * Replaces ROM content * Can also be used to implement embedded debug support * Automatic transfer function independent of CPU, can be assigned freely to resources * Fast Interrupt processing * 8 programmable priority levels * Non-Maskable Interrupt (NMI) Timers * Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) * Watchdog Timer Description
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FME-MB96350 rev 7
MB96350 Series
Feature * ISO16845 certified * Bit rates up to 1 Mbit/s * 32 message objects CAN * Each message object has its own identifier mask * Programmable FIFO mode (concatenation of message objects) * Maskable interrupt * Disabled Automatic Retransmission mode for Time Triggered CAN applications * Programmable loop-back mode for self-test operation * Full duplex USARTs (SCI/LIN) USART * Wide range of baud rate settings using a dedicated reload timer * Special synchronous options for adapting to different synchronous serial protocols * LIN functionality working either as master or slave LIN device I2C * Up to 400 kbps * Master and Slave functionality, 7-bit and 10-bit addressing * SAR-type A/D converter * 10-bit resolution * Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer * 16-bit wide Reload Timers * Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency * Event count function Free Running Timers * Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of peripheral clock frequency * 16-bit wide Input Capture Units * Signals an interrupt upon external event * Rising edge, falling edge or rising & falling edge sensitive * 16-bit wide Output Compare Units * Signals an interrupt when a match with 16-bit I/O Timer occurs * A pair of compare registers can be used to generate an output signal. * 16-bit down counter, cycle and duty setting registers * Interrupt at trigger, counter borrow and/or duty match Programmable Pulse Generator * PWM operation and one-shot operation * Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and Reload timer underflow as clock input * Can be triggered by software or reload timer Description * Supports CAN protocol version 2.0 part A and B
FME-MB96350 rev 7
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MB96350 Series
Feature Description * Can be clocked either from sub oscillator (devices with part number suffix "W"), main oscillator or from the RC oscillator Real Time Clock * Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration) * Read/write accessible second/minute/hour registers * Can signal interrupts every half second/second/minute/hour/day * Internal clock divider and prescaler provide exact 1s clock * Edge sensitive or level sensitive External Interrupts * Interrupt mask and pending bit per channel * Each available CAN channel RX has an external interrupt for wake-up * Selected USART channels SIN have an external interrupt for wake-up * Disabled after reset Non Maskable Interrupt * Once enabled, can not be disabled other than by reset. * Level high or level low sensitive * Pin shared with external interrupt 0. * 8-bit or 16-bit bidirectional data * Up to 24-bit addresses * 6 chip select signals External bus interface * Multiplexed address/data lines * Wait state request * External bus master possible * Timing programmable * Virtually all external pins can be used as general purpose I/O * All push-pull outputs (except when used as I2C SDA/SCL line) * Bit-wise programmable as input/output or peripheral signal I/O Ports * Bit-wise programmable input enable * Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL * Bit-wise programmable pull-up resistor * Bit-wise programmable output driving strength for EMI optimization Packages * 64-pin plastic LQFP M23/M24
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FME-MB96350 rev 7
MB96350 Series
Feature Description * Supports automatic programming, Embedded Algorithm * Write/Erase/Erase-Suspend/Resume commands * A flag indicating completion of the algorithm * Number of erase cycles: 10,000 times Flash Memory * Data retention time: 20 years * Erase can be performed on each sector individually * Sector protection * Flash Security feature to protect the content of the Flash * Low voltage detection during Flash erase
FME-MB96350 rev 7
5
MB96350 Series
PRODUCT LINEUP
Features Product type Product options YS RS YW
MB96V300B Evaluation sample
MB96(F)35x Flash product: MB96F35x Mask ROM product: MB9635x
Low voltage reset persistently on / Single clock devices Low voltage reset can be disabled / Single clock devices Low voltage reset persistently on / Dual clock devices NA Low voltage reset can be disabled / Dual clock devices No CAN / Low voltage reset can be disabled / Single clock devices No CAN / Low voltage reset can be disabled / Dual clock devices RAM 8KB 8KB 12KB ROM/Flash memory emulation by external RAM, 92KB internal RAM BGA416 16 channels 10 channels 2 channels 40 channels yes 6 channels + 1 channel (for PPG) 4 channels 12 channels 12 channels 20 channels MB96F353R, MB96F353A MB96F355R, MB96F355A MB96F356Y, MB96F356R, MB96F356A FPT-64P-M23/24 4 channels 4 channels 1 channel 15 channels No 4 channels + 1 channel (for PPG) 4 channels (2 channels with external clock input pin) 4 channels 6 channels (plus 2 channels for LIN USART) 20 channels MB96F35xA: no MB96F353R/F355R: 1 channel MB96F356Y/R: 2 channels 13 channels 1 channel
RW AS AW Flash/ ROM 96KB 160KB 288KB Package DMA USART I2C A/D Converter A/D Converter Reference Voltage switch 16-bit Reload Timer 16-bit Free-Running Timer 16-bit Output Compare 16-bit Input Capture 16-bit Programmable Pulse Generator CAN Interface External Interrupts Non-Maskable Interrupt
5 channels 16 channels
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FME-MB96350 rev 7
MB96350 Series
Features Real Time Clock I/O Ports External bus interface Chip select Clock output function Low voltage reset On-chip RC-oscillator 136 MB96V300B 1 49 for part number with suffix "W", 51 for part number with suffix "S" Yes 6 signals 2 channels Yes Yes MB96(F)35x
FME-MB96350 rev 7
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MB96350 Series
BLOCK DIAGRAM
Block diagram of MB96(F)35x
AD00 ... AD15 A16 ... A21 ALE RDX WR(L)X, WRHX HRQ HAKX RDY ECLK CS0_R ... CS5_R
External Bus Interface
16FX CPU
NMI_R
CKOT0_R, CKOT1, CKOT1_R CKOTX1 X0, X1 X0A, X1A *1 RSTX MD0...MD2
Interrupt Controller
Flash Memory A
Memory Patch Unit
Clock & Mode Controller
16FX Core Bus (CLKB)
DMA Controller
Watchdog
Peripheral Bus Bridge
Peripheral Bus Bridge
RAM
Boot ROM
Voltage Regulator
Peripheral Bus 2 (CLKP2)
SDA0 SCL0 AVCC AVSS AVRH AN0 ... AN14 ADTG_R TIN0_R, TIN2_R TIN1, TIN3 TOT0_R, TOT2_R TOT1, TOT3 FRCK0 IN0 ... IN1 FRCK1 IN4 ... IN7 OUT4 ... OUT7
I2C 1 ch.
VCC VSS C CAN Interface 2 ch. TX1 *2, TX2 *3 RX1*2 , RX2 *3
10-bit ADC 15 ch. Peripheral Bus 1 (CLKP1)
16-bit Reload Timer 4 ch.
USART 4 ch.
SIN2, SIN2_R, SIN3, SIN7_R, SIN8_R SOT2, SOT2_R, SOT3, SOT7_R, SOT8_R SCK2, SCK2_R, SCK3, SCK7_R, SCK8_R TTG0, TTG1, TTG4 ... TTG9, TTG12 ... TTG15 TTG8_R ... TTG11_R, TTG16_R ... TTG19_R PPG0 ... PPG7, PPG12 ... PPG15 PPG8_R ... PPG11_R, PPG16_R ... PPG19_R
I/O Timer 0 ICU 0/1 I/O Timer 1 ICU 4/5/6/7 OCU 4/5/6/7 I/O Timer 2 ICU 9 I/O Timer 3 ICU 10
16-bit PPG 20 ch. RLT6 Real Time Clock
WOT
External Interrupt
INT8 ... INT15 INT0_R, INT2_R, INT4_R INT7_R, INT9_R ... INT11_R INT3_R1
*1: X0A, X1A only available on devices with suffix "W" *2: TX1, RX1 only available on MB96F356Y/R *3: TX2, RX2 only available on MB96F356Y/R and MB96F353R/F355R
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FME-MB96350 rev 7
MB96350 Series
PIN ASSIGNMENTS
Pin assignment of MB96(F)35x
P01_5/AD13/SIN2_R/INT7_R/PPG17_R
Vcc C P02_5/A21/TTG9/TTG1/IN1/ADTG_R P04_4/SDA0/FRCK0/TIN0_R P04_5/SCL0/FRCK1/TIN2_R P03_0/ALE/IN4/TTG4/TTG12/TOT0_R P03_1/RDX/IN5/TTG5/TTG13/TOT2_R P03_2/WR(L)X/RX2/INT10_R P03_3/TX2/WRHX
*3 *3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 AVss 2 AVRH 3 P06_2/AN2/PPG2/CS2_R 4 P06_3/AN3/PPG3/CS3_R 5 P06_4/AN4/PPG4/CS4_R 6 P06_5/AN5/PPG5/CS5_R 7 P06_6/AN6/PPG6 8 P06_7/AN7/PPG7 31 30 29
P01_1/AD09/CKOTX1/TOT1/TTG17_R
P01_2/AD10/INT11_R/SIN3/TTG18_R
P01_6/AD14/SOT2_R/PPG18_R
P01_7/AD15/SCK2_R/PPG19_R
P02_2/A18/PPG14/CKOT0_R
P02_0/A16/PPG12/CKOT1_R
P01_4/AD12/SCK3/PPG16_R
P01_3/AD11/SOT3/TTG19_R
P02_4/A20/TTG8/TTG0/IN0
P02_3/A19/PPG15
P02_1/A17/PPG13
RSTX
Vss
X0
X1
P01_0/AD08/CKOT1/TIN1/TTG16_R P00_7/AD07/INT15/PPG11_R P00_6/AD06/INT14/PPG10_R P00_5/AD05/INT13/SIN8_R/PPG9_R P00_4/AD04/INT12/SOT8_R/PPG8_R P00_3/AD03/INT11/SCK8_R/TTG11_R P00_2/AD02/INT10/SIN7_R/TTG10_R P00_1/AD01/INT9/SOT7_R/TTG9_R P00_0/AD00/INT8/SCK7_R/TTG8_R MD0 MD1 MD2 X1A/P04_1 *1 X0A/P04_0 Vss P04_3/IN7/TX1/TTG7/TTG15
*2 *1
LQFP - 64
Package code (mold) FPT-64P-M23/M24
28 27 26 25 24 23 22 21 20 19 18
P03_4/HRQ/OUT4 P03_5/HAKX/OUT5 P03_6/RDY/OUT6 P03_7/ECLK/OUT7 P06_0/AN0/PPG0/CS0_R P06_1/AN1/PPG1/CS1_R AVcc
17 9 10 11 12 13 14 15 16 P05_4/AN12/TOT3/INT2_R P05_3/AN11/TIN3/WOT P05_6/AN14/INT4_R P05_2/AN10/SCK2 P05_1/AN9/SOT2 P05_5/AN13/INT0_R/NMI_R P05_0/AN8/SIN2/INT3_R1
*2
*1: Devices with suffix W: X0A, X1A Devices with suffix S: P04_0, P04_1 *2: TX1, RX1 only available on MB96F356Y/R *3: TX2, RX2 only available on MB96F356Y/R and MB96F353R/F355R
(FPT-64P-M23/M24)
Remark: MB96(F)35x products are pin-compatible to F2MC-16LX family MB90350 series.
FME-MB96350 rev 7
P04_2/IN6/RX1/INT9_R/TTG6/TTG14
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MB96350 Series
PIN FUNCTION DESCRIPTION
Pin Function description (1 of 2) Pin name ADn ADTG_R ALE An ANn AVCC AVRH AVSS C CKOTn CKOTn_R CKOTXn ECLK CSn_R FRCKn HAKX HRQ INn INTn INTn_R MDn NMI_R OUTn Pxx_n PPGn PPGn_R RDX RDY Feature External bus ADC External bus External bus ADC Supply ADC Supply Voltage regulator Clock output function Clock output function Clock output function External bus External bus Free Running Timer External bus External bus ICU External Interrupt External Interrupt Core External Interrupt OCU GPIO PPG PPG External bus External bus Description External bus interface (multiplexed mode) address output and data input/output Relocated A/D converter trigger input External bus Address Latch Enable output External bus address output A/D converter channel n input Analog circuits power supply A/D converter high reference voltage input Analog circuits power supply Internally regulated power supply stabilization capacitor pin Clock Output function n output Relocated Clock Output function n output Clock Output function n inverted output External bus clock output Relocated External bus chip select n output Free Running Timer n input External bus Hold Acknowledge External bus Hold Request Input Capture Unit n input External Interrupt n input Relocated External Interrupt n input Input pins for specifying the operating mode. Relocated Non-Maskable Interrupt input Output Compare Unit n waveform output General purpose IO Programmable Pulse Generator n output Relocated Programmable Pulse Generator n output External bus interface read strobe output External bus interface external wait state request input
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FME-MB96350 rev 7
MB96350 Series
Pin Function description (2 of 2) Pin name RSTX RXn SCKn SCKn_R SCLn SDAn SINn SINn_R SOTn SOTn_R TINn TINn_R TOTn TOTn_R TTGn TTGn_R TXn VCC VSS WOT WRHX WRLX/WRX X0 X0A X1 X1A Feature Core CAN USART USART I2C I2C USART USART USART USART Reload Timer Reload Timer Reload Timer Reload Timer PPG PPG CAN Supply Supply RTC External bus External bus Clock Clock Clock Clock Description Reset input CAN interface n RX input USART n serial clock input/output Relocated USART n serial clock input/output I2C interface n clock I/O input/output I2C interface n serial data I/O input/output USART n serial data input Relocated USART n serial data input USART n serial data output Relocated USART n serial data output Reload Timer n event input Relocated Reload Timer n event input Reload Timer n output Relocated Reload Timer n output Programmable Pulse Generator n trigger input Relocated Programmable Pulse Generator n trigger input CAN interface n TX output Power supply Power supply Real Timer clock output External bus High byte write strobe output External bus Low byte / Word write strobe output Oscillator input Subclock Oscillator input (only for devices with suffix "W") Oscillator output Subclock Oscillator output (only for devices with suffix "W")
FME-MB96350 rev 7
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MB96350 Series
PIN CIRCUIT TYPE
Pin circuit types
FPT-64P-M23/24 Pin no. 1 2 3 to 15 16,17 18 19,20 19,20 21 to 23 24 to 44 45 46,47 48,49 50 51 52,53 54 to 61 62,63 64 Circuit
type *1
Supply G I H Supply
B *2 H *3
C H E A Supply F H N H I Supply
*1: Please refer to " I/O CIRCUIT TYPE" for details on the I/O circuit types *2: Devices with suffix "W" *3: Devices without suffix "W"
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FME-MB96350 rev 7
MB96350 Series
I/O CIRCUIT TYPE
Type A
X1
R
Circuit
Remarks High-speed oscillation circuit: * Programmable between oscillation mode (external crystal or resonator connected to X0/X1 pins) and Fast external Clock Input (FCI) mode (external clock connected to X0 pin) * Programmable feedback resistor = approx. 2 * 0.5 M. Feedback resistor is grounded in the center when the oscillator is disabled or in FCI mode
0 MRFBE 1
Xout
R
FCI
X0
FCI or osc disable
B
X1A
R
Xout
Low-speed oscillation circuit: * Programmable feedback resistor = approx. 2 * 5 M. Feedback resistor is grounded in the center when the oscillator is disabled
SRFBE
R
X0A
osc disable
C
R Hysteresis inputs
* Mask ROM and EVA device: CMOS Hysteresis input pin * Flash device: CMOS input pin * CMOS Hysteresis input pin * Pull-up resistor value: approx. 50 k
E
Pull-up Resistor R Hysteresis inputs
FME-MB96350 rev 7
13
MB96350 Series
Type F Circuit Remarks * Power supply input protection circuit
G
ANE AVR ANE
* A/D converter ref+ (AVRH) power supply input pin with protection circuit * Flash devices do not have a protection circuit against VCC for pin AVRH
H
pull-up control
Pout
Nout R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Hysteresis input
* CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) * 2 different CMOS hysteresis inputs with input shutdown function * Automotive input with input shutdown function * TTL input with input shutdown function * Programmable pull-up resistor: 50k approx. Note: MB96F353/F355: Only Automotive input and CMOS hysteresis input (0.7/0.3) are supported
Hysteresis input
Automotive input
TTL input
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FME-MB96350 rev 7
MB96350 Series
Type I
Pull-up control
Circuit
Remarks * CMOS level output (programmable IOL = 5mA, IOH = -5mA and IOL = 2mA, IOH = -2mA) * 2 different CMOS hysteresis inputs with input shutdown function * Automotive input with input shutdown function * TTL input with input shutdown function. * Programmable pull-up resistor: 50k approx. * Analog input Note: MB96F353/F355: Only Automotive input and CMOS hysteresis input (0.7/0.3) are supported
Pout
Nout R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Hysteresis input
Hysteresis input
Automotive input
TTL input Analog input
N
pull-up control
Pout
* CMOS level output (IOL = 3mA, IOH = -3mA) * 2 different CMOS hysteresis inputs with input shutdown function * Automotive input with input shutdown function * TTL input with input shutdown function * Programmable pull-up resistor: 50k approx. *1: N-channel transistor has slew rate control according to I2C spec, irrespective of usage
Nout R Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Standby control for input shutdown Hysteresis input
Hysteresis input
Note: MB96F353/F355: Only Automotive input and CMOS hysteresis input (0.7/0.3) are supported
Automotive input
TTL input
FME-MB96350 rev 7
15
MB96350 Series
MEMORY MAP
MB96V300B
FF:FFFFH
MB96(F)35x
Emulation ROM
DE:0000H
USER ROM / External Bus*4
External Bus
External Bus
10:0000H 0F:E000H
Boot-ROM
Boot-ROM
Reserved
0E:0000H
Reserved External RAM
02:0000H
Internal RAM bank 1
01:0000H
RAMEND1*2 RAMSTART12
Reserved Internal RAM bank 1 Reserved ROM/RAM MIRROR Internal RAM bank 0 Reserved
RAM availability depending on the device
ROM/RAM MIRROR
00:8000H
Internal RAM bank 0
RAMSTART0*3
00:0C00H
RAMSTART0
*2
External Bus end address*2 External Bus
External Bus Peripherals Peripherals GPR*1 DMA External Bus Peripheral
00:0380H 00:0180H 00:0100H 00:00F0H 00:0000H
GPR*1 DMA External Bus Peripheral
*1: Unused GPR banks can be used as RAM area *2: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page. *3: For EVA device, RAMSTART0 depends on the configuration of the emulated device. *4: For details about USER ROM area, see the USER ROM MEMORY MAP FOR FLASH DEVICES on the following pages. The External Bus area and DMA area are only available if the device contains the corresponding resource. The available RAM and ROM area depends on the device.
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FME-MB96350 rev 7
MB96350 Series
RAMSTART/END AND EXTERNAL BUS END ADDRESSES
Devices MB96F353/F355 MB96F356 Bank 0 Bank 1 External Bus RAM size RAM size end address 8KByte 12KByte 00:51FFH 00:51FFH RAMSTART0 00:6240H 00:5240H RAMSTART1 RAMEND1 -
FME-MB96350 rev 7
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MB96350 Series
USER ROM MEMORY MAP FOR FLASH DEVICES
MB96F353
Alternative mode CPU address
FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH FD:0000H FC:FFFFH FC:0000H FB:FFFFH FB:0000H FA:FFFFH FA:0000H F9:FFFFH F9:0000H F8:FFFFH F8:0000H F7:FFFFH F7:0000H F6:FFFFH F6:0000H F5:FFFFH F5:0000H F4:FFFFH F4:0000H F3:FFFFH F3:0000H F2:FFFFH F2:0000H F1:FFFFH F1:0000H F0:FFFFH F0:0000H E0:FFFFH
MB96F355
Flash size 160kByte
MB96F356
Flash size 288kByte
Flash memory mode address
3F:FFFFH 3F:0000H 3E:FFFFH 3E:0000H 3D:FFFFH 3D:0000H 3C:FFFFH 3C:0000H 3B:FFFFH 3B:0000H 3A:FFFFH 3A:0000H 39:FFFFH 39:0000H 38:FFFFH 38:0000H 37:FFFFH 37:0000H 36:FFFFH 36:0000H 35:FFFFH 35:0000H 34:FFFFH 34:0000H 33:FFFFH 33:0000H 32:FFFFH 32:0000H 31:FFFFH 31:0000H 30:FFFFH 30:0000H
Flash size 96kByte
S39 - 64K
S39 - 64K S38 - 64K
S39 - 64K S38 - 64K S37 - 64K S36 - 64K
Flash A
External bus
External bus External bus
E0:0000H DF:FFFFH DF:8000H DF:7FFFH DF:6000H DF:5FFFH DF:4000H DF:3FFFH DF:2000H DF:1FFFH DF:0000H DE:FFFFH DE:0000H
Reserved
1F:7FFFH 1F:6000H 1F:5FFFH 1F:4000H 1F:3FFFH 1F:2000H 1F:1FFFH 1F:0000H
Reserved SA3 - 8K SA2 - 8K SA1 - 8K SA0 - 8K *1 Reserved
Reserved SA3 - 8K SA2 - 8K SA1 - 8K SA0 - 8K *1 Reserved
SA3 - 8K SA2 - 8K SA1 - 8K SA0 - 8K *1 Reserved
Flash A
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
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FME-MB96350 rev 7
MB96350 Series
SERIAL PROGRAMMING COMMUNICATION INTERFACE
USART pins for Flash serial programming (MD[2:0] = 010) MB96F35x Pin number USART Number LQFP-64 9 10 11 34 35 36 26 25 24 29 28 27 USART8 USART7 USART3 USART2 SIN2 SOT2 SCK2 SIN3 SOT3 SCK3 SIN7_R SOT7_R SCK7_R SIN8_R SOT8_R SCK8_R Normal function
Note: If a Flash programmer and its software needs to use a handshaking pin, Fujitsu suggests to the tool vendor to support at least port P00_1 on pin 25. If handshaking is used by the tool but P00_1 is not available in customer's application, Fujitsu suggests to the customer to check the tool manual or to contact the tool vendor for alternative handshaking pins.
FME-MB96350 rev 7
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MB96350 Series
I/O MAP
I/O map MB96(F)35x (1 of 28) Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H000033H Register I/O Port P00 - Port Data Register I/O Port P01 - Port Data Register I/O Port P02 - Port Data Register I/O Port P03 - Port Data Register I/O Port P04 - Port Data Register I/O Port P05 - Port Data Register I/O Port P06 - Port Data Register Reserved ADC0 - Control Status register Low ADC0 - Control Status register High ADC0 - Data Register Low ADC0 - Data Register High ADC0 - Setting Register ADC0 - Setting Register ADC0 - Extended Configuration Register Reserved FRT0 - Data register of free-running timer FRT0 - Data register of free-running timer FRT0 - Control status register of free-running timer Low FRT0 - Control status register of free-running timer High FRT1 - Data register of free-running timer FRT1 - Data register of free-running timer FRT1 - Control status register of free-running timer Low FRT1 - Control status register of free-running timer High Reserved TCCSL1 TCCSH1 TCCS1 TCCSL0 TCCSH0 TCDT1 TCCS0 TCDT0 ADECR ADCSL ADCSH ADCRL ADCRH ADSR ADCR ADCS Abbreviation 8-bit access PDR00 PDR01 PDR02 PDR03 PDR04 PDR05 PDR06 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -
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FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (2 of 28) Address 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H Register OCU4 - Output Compare Control Status OCU5 - Output Compare Control Status OCU4 - Compare Register OCU4 - Compare Register OCU5 - Compare Register OCU5 - Compare Register OCU6 - Output Compare Control Status OCU7 - Output Compare Control Status OCU6 - Compare Register OCU6 - Compare Register OCU7 - Compare Register OCU7 - Compare Register ICU0/ICU1 - Control Status Register ICU0/ICU1 - Edge register ICU0 - Capture Register Low ICU0 - Capture Register High ICU1 - Capture Register Low ICU1 - Capture Register High Reserved ICU4/ICU5 - Control Status Register ICU4/ICU5 - Edge register ICU4 - Capture Register Low ICU4 - Capture Register High ICU5 - Capture Register Low ICU5 - Capture Register High ICU6/ICU7 - Control Status Register ICU6/ICU7 - Edge register ICU6 - Capture Register Low ICU6 - Capture Register High ICS45 ICE45 IPCPL4 IPCPH4 IPCPL5 IPCPH5 ICS67 ICE67 IPCPL6 IPCPH6 IPCP6 IPCP5 IPCP4 R/W R/W R R R R R/W R/W R R ICS01 ICE01 IPCPL0 IPCPH0 IPCPL1 IPCPH1 IPCP1 IPCP0 OCCP7 OCS6 OCS7 OCCP6 OCCP5 Abbreviation 8-bit access OCS4 OCS5 OCCP4 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
FME-MB96350 rev 7
21
MB96350 Series
I/O map MB96(F)35x (3 of 28) Address 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000062H 000063H 000063H 000064H 000065H 000066H 000066H 000067H 000067H 000068H 000069H 00006AH 00006AH 00006BH 00006BH 00006CH Register ICU7 - Capture Register Low ICU7 - Capture Register High EXTINT0 - External Interrupt Enable Register EXTINT0 - External Interrupt Interrupt request Register EXTINT0 - External Interrupt Level Select Low EXTINT0 - External Interrupt Level Select High EXTINT1 - External Interrupt Enable Register EXTINT1 - External Interrupt Interrupt request Register EXTINT1 - External Interrupt Level Select Low EXTINT1 - External Interrupt Level Select High RLT0 - Timer Control Status Register Low RLT0 - Timer Control Status Register High RLT0 - Reload Register - for writing RLT0 - Reload Register - for reading RLT0 - Reload Register - for writing RLT0 - Reload Register - for reading RLT1 - Timer Control Status Register Low RLT1 - Timer Control Status Register High RLT1 - Reload Register - for writing RLT1 - Reload Register - for reading RLT1 - Reload Register - for writing RLT1 - Reload Register - for reading RLT2 - Timer Control Status Register Low RLT2 - Timer Control Status Register High RLT2 - Reload Register - for writing RLT2 - Reload Register - for reading RLT2 - Reload Register - for writing RLT2 - Reload Register - for reading RLT3 - Timer Control Status Register Low TMCSRL3 TMCSR3 TMCSRL2 TMCSRH2 TMRLR2 TMR2 TMCSR2 TMCSRL1 TMCSRH1 TMRLR1 TMR1 TMCSR1 Abbreviation 8-bit access IPCPL7 IPCPH7 ENIR0 EIRR0 ELVRL0 ELVRH0 ENIR1 EIRR1 ELVRL1 ELVRH1 TMCSRL0 TMCSRH0 TMRLR0 TMR0 TMCSR0 ELVR1 ELVR0 Abbreviation 16-bit access IPCP7 Access R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R W R R/W R/W W R W R R/W R/W W R W R R/W
22
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (4 of 28) Address 00006DH 00006EH 00006EH 00006FH 00006FH 000070H 000071H 000072H 000072H 000073H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H Register RLT3 - Timer Control Status Register High RLT3 - Reload Register - for writing RLT3 - Reload Register - for reading RLT3 - Reload Register - for writing RLT3 - Reload Register - for reading RLT6 - Timer Control Status Register Low (dedic. RLT for PPG) RLT6 - Timer Control Status Register High (dedic. RLT for PPG) RLT6 - Reload Register (dedic. RLT for PPG) - for writing RLT6 - Reload Register (dedic. RLT for PPG) - for reading RLT6 - Reload Register (dedic. RLT for PPG) - for writing RLT6 - Reload Register (dedic. RLT for PPG) - for reading PPG3-PPG0 - General Control register 1 Low PPG3-PPG0 - General Control register 1 High PPG3-PPG0 - General Control register 2 Low PPG3-PPG0 - General Control register 2 High PPG0 - Timer register PPG0 - Timer register PPG0 - Period setting register PPG0 - Period setting register PPG0 - Duty cycle register PPG0 - Duty cycle register PPG0 - Control status register Low PPG0 - Control status register High PPG1 - Timer register PPG1 - Timer register PPG1 - Period setting register PCSR1 PCNL0 PCNH0 PTMR1 PCN0 PDUT0 PCSR0 GCN1L0 GCN1H0 GCN2L0 GCN2H0 PTMR0 GCN20 GCN10 TMCSRL6 TMCSRH6 TMRLR6 TMR6 TMCSR6 Abbreviation 8-bit access TMCSRH3 TMRLR3 TMR3 Abbreviation 16-bit access Access R/W W R W R R/W R/W W R W R R/W R/W R/W R/W R R W W W W R/W R/W R R W
FME-MB96350 rev 7
23
MB96350 Series
I/O map MB96(F)35x (5 of 28) Address 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 000090H 000091H 000092H 000093H 000094H 000095H 000096H 000097H 000098H 000099H 00009AH 00009BH 00009CH 00009DH 00009EH 00009FH 0000A0H Register PPG1 - Period setting register PPG1 - Duty cycle register PPG1 - Duty cycle register PPG1 - Control status register Low PPG1 - Control status register High PPG2 - Timer register PPG2 - Timer register PPG2 - Period setting register PPG2 - Period setting register PPG2 - Duty cycle register PPG2 - Duty cycle register PPG2 - Control status register Low PPG2 - Control status register High PPG3 - Timer register PPG3 - Timer register PPG3 - Period setting register PPG3 - Period setting register PPG3 - Duty cycle register PPG3 - Duty cycle register PPG3 - Control status register Low PPG3 - Control status register High PPG7-PPG4 - General Control register 1 Low PPG7-PPG4 - General Control register 1 High PPG7-PPG4 - General Control register 2 Low PPG7-PPG4 - General Control register 2 High PPG4 - Timer register PPG4 - Timer register PPG4 - Period setting register PPG4 - Period setting register PPG4 - Duty cycle register PDUT4 PCSR4 PCNL3 PCNH3 GCN1L1 GCN1H1 GCN2L1 GCN2H1 PTMR4 GCN21 GCN11 PCN3 PDUT3 PCSR3 PCNL2 PCNH2 PTMR3 PCN2 PDUT2 PCSR2 PCNL1 PCNH1 PTMR2 PCN1 PDUT1 Abbreviation 8-bit access Abbreviation 16-bit access Access W W W R/W R/W R R W W W W R/W R/W R R W W W W R/W R/W R/W R/W R/W R/W R R W W W
24
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (6 of 28) Address 0000A1H 0000A2H 0000A3H 0000A4H 0000A5H 0000A6H 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH 0000ACH 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H0000D3H 0000D4H 0000D5H 0000D6H 0000D6H 0000D7H 0000D8H 0000D9H Register PPG4 - Duty cycle register PPG4 - Control status register Low PPG4 - Control status register High PPG5 - Timer register PPG5 - Timer register PPG5 - Period setting register PPG5 - Period setting register PPG5 - Duty cycle register PPG5 - Duty cycle register PPG5 - Control status register Low PPG5 - Control status register High I2C0 - Bus Status Register I2C0 - Bus Control Register I2C0 - Ten bit Slave address Register Low I2C0 - Ten bit Slave address Register High I2C0 - Ten bit Address mask Register Low I2C0 - Ten bit Address mask Register High I2C0 - Seven bit Slave address Register I2C0 - Seven bit Address mask Register I2C0 - Data Register I2C0 - Clock Control Register Reserved USART2 - Serial Mode Register USART2 - Serial Control Register USART2 - TX Register USART2 - RX Register USART2 - Serial Status USART2 - Control/Com. Register USART2 - Ext. Status Register SMR2 SCR2 TDR2 RDR2 SSR2 ECCR2 ESCR2 PCNL5 PCNH5 IBSR0 IBCR0 ITBAL0 ITBAH0 ITMKL0 ITMKH0 ISBA0 ISMK0 IDAR0 ICCR0 ITMK0 ITBA0 PCN5 PDUT5 PCSR5 PCNL4 PCNH4 PTMR5 PCN4 Abbreviation 8-bit access Abbreviation 16-bit access Access W R/W R/W R R W W W W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R R/W R/W R/W
FME-MB96350 rev 7
25
MB96350 Series
I/O map MB96(F)35x (7 of 28) Address 0000DAH 0000DBH 0000DCH 0000DDH 0000DEH 0000DFH 0000E0H 0000E0H 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H 0000E6H 0000E7H0000EFH 0000F0H0000FFH 000100H 000101H 000102H 000103H 000104H 000105H 000106H 000107H 000108H 000109H 00010AH 00010BH 00010CH Register USART2 - Baud Rate Generator Register Low USART2 - Baud Rate Generator Register High USART2 - Extended Serial Interrupt Register Reserved USART3 - Serial Mode Register USART3 - Serial Control Register USART3 - TX Register USART3 - RX Register USART3 - Serial Status USART3 - Control/Com. Register USART3 - Ext. Status Register USART3 - Baud Rate Generator Register Low USART3 - Baud Rate Generator Register High USART3 - Extended Serial Interrupt Register Reserved External Bus area DMA0 - Buffer address pointer low byte DMA0 - Buffer address pointer middle byte DMA0 - Buffer address pointer high byte DMA0 - DMA control register DMA0 - I/O register address pointer low byte DMA0 - I/O register address pointer high byte DMA0 - Data counter low byte DMA0 - Data counter high byte DMA1 - Buffer address pointer low byte DMA1 - Buffer address pointer middle byte DMA1 - Buffer address pointer high byte DMA1 - DMA control register DMA1 - I/O register address pointer low byte EXTBUS0 BAPL0 BAPM0 BAPH0 DMACS0 IOAL0 IOAH0 DCTL0 DCTH0 BAPL1 BAPM1 BAPH1 DMACS1 IOAL1 IOA1 DCT0 IOA0 SMR3 SCR3 TDR3 RDR3 SSR3 ECCR3 ESCR3 BGRL3 BGRH3 ESIR3 BGR3 Abbreviation 8-bit access BGRL2 BGRH2 ESIR2 Abbreviation 16-bit access BGR2 Access R/W R/W R/W R/W R/W W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
26
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (8 of 28) Address 00010DH 00010EH 00010FH 000110H 000111H 000112H 000113H 000114H 000115H 000116H 000117H 000118H 000119H 00011AH 00011BH 00011CH 00011DH 00011EH 00011FH 000120H00017FH 000180H00037FH 000380H 000381H 000382H 000383H 000384H00038FH 000390H 000391H Register DMA1 - I/O register address pointer high byte DMA1 - Data counter low byte DMA1 - Data counter high byte DMA2 - Buffer address pointer low byte DMA2 - Buffer address pointer middle byte DMA2 - Buffer address pointer high byte DMA2 - DMA control register DMA2 - I/O register address pointer low byte DMA2 - I/O register address pointer high byte DMA2 - Data counter low byte DMA2 - Data counter high byte DMA3 - Buffer address pointer low byte DMA3 - Buffer address pointer middle byte DMA3 - Buffer address pointer high byte DMA3 - DMA control register DMA3 - I/O register address pointer low byte DMA3 - I/O register address pointer high byte DMA3 - Data counter low byte DMA3 - Data counter high byte Reserved CPU - General Purpose registers (RAM access) DMA0 - Interrupt select DMA1 - Interrupt select DMA2 - Interrupt select DMA3 - Interrupt select Reserved DMA - Status register low byte DMA - Status register high byte DSRL DSRH DSR GPR_RAM DISEL0 DISEL1 DISEL2 DISEL3 Abbreviation 8-bit access IOAH1 DCTL1 DCTH1 BAPL2 BAPM2 BAPH2 DMACS2 IOAL2 IOAH2 DCTL2 DCTH2 BAPL3 BAPM3 BAPH3 DMACS3 IOAL3 IOAH3 DCTL3 DCTH3 DCT3 IOA3 DCT2 IOA2 DCT1 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FME-MB96350 rev 7
27
MB96350 Series
I/O map MB96(F)35x (9 of 28) Address 000392H 000393H 000394H 000395H 000396H00039FH 0003A0H 0003A1H 0003A2H 0003A3H 0003A4H 0003A5H 0003A6H0003ABH 0003ACH 0003ADH 0003AEH 0003AFH 0003B0H 0003B1H 0003B2H 0003B3H 0003B4H 0003B5H 0003B6H 0003B7H 0003B8H 0003B9H 0003BAH 0003BBH 0003BCH Register DMA - Stop status register low byte DMA - Stop status register high byte DMA - Enable register low byte DMA - Enable register high byte Reserved Interrupt level register Interrupt index register Interrupt vector table base register Low Interrupt vector table base register High Delayed Interrupt register Non Maskable Interrupt register Reserved EDSU communication interrupt selection Low EDSU communication interrupt selection High ROM mirror control register EDSU configuration register Memory patch control/status register ch 0/1 Memory patch control/status register ch 0/1 Memory patch control/status register ch 2/3 Memory patch control/status register ch 2/3 Memory patch control/status register ch 4/5 Memory patch control/status register ch 4/5 Memory patch control/status register ch 6/7 Memory patch control/status register ch 6/7 Memory Patch function - Patch address 0 low Memory Patch function - Patch address 0 middle Memory Patch function - Patch address 0 high Memory Patch function - Patch address 1 low Memory Patch function - Patch address 1 middle PFAL0 PFAM0 PFAH0 PFAL1 PFAM1 PFCS3 PFCS2 PFCS1 EDSU2L EDSU2H ROMM EDSU PFCS0 EDSU2 ILR IDX TBRL TBRH DIRR NMI TBR ICR Abbreviation 8-bit access DSSRL DSSRH DERL DERH DER Abbreviation 16-bit access DSSR Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
28
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (10 of 28) Address 0003BDH 0003BEH 0003BFH 0003C0H 0003C1H 0003C2H 0003C3H 0003C4H 0003C5H 0003C6H 0003C7H 0003C8H 0003C9H 0003CAH 0003CBH 0003CCH 0003CDH 0003CEH 0003CFH 0003D0H 0003D1H 0003D2H 0003D3H 0003D4H 0003D5H 0003D6H 0003D7H 0003D8H 0003D9H 0003DAH Register Memory Patch function - Patch address 1 high Memory Patch function - Patch address 2 low Memory Patch function - Patch address 2 middle Memory Patch function - Patch address 2 high Memory Patch function - Patch address 3 low Memory Patch function - Patch address 3 middle Memory Patch function - Patch address 3 high Memory Patch function - Patch address 4 low Memory Patch function - Patch address 4 middle Memory Patch function - Patch address 4 high Memory Patch function - Patch address 5 low Memory Patch function - Patch address 5 middle Memory Patch function - Patch address 5 high Memory Patch function - Patch address 6 low Memory Patch function - Patch address 6 middle Memory Patch function - Patch address 6 high Memory Patch function - Patch address 7 low Memory Patch function - Patch address 7 middle Memory Patch function - Patch address 7 high Memory Patch function - Patch data 0 Low Memory Patch function - Patch data 0 High Memory Patch function - Patch data 1 Low Memory Patch function - Patch data 1 High Memory Patch function - Patch data 2 Low Memory Patch function - Patch data 2 High Memory Patch function - Patch data 3 Low Memory Patch function - Patch data 3 High Memory Patch function - Patch data 4 Low Memory Patch function - Patch data 4 High Memory Patch function - Patch data 5 Low Abbreviation 8-bit access PFAH1 PFAL2 PFAM2 PFAH2 PFAL3 PFAM3 PFAH3 PFAL4 PFAM4 PFAH4 PFAL5 PFAM5 PFAH5 PFAL6 PFAM6 PFAH6 PFAL7 PFAM7 PFAH7 PFDL0 PFDH0 PFDL1 PFDH1 PFDL2 PFDH2 PFDL3 PFDH3 PFDL4 PFDH4 PFDL5 PFD5 PFD4 PFD3 PFD2 PFD1 PFD0 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FME-MB96350 rev 7
29
MB96350 Series
I/O map MB96(F)35x (11 of 28) Address 0003DBH 0003DCH 0003DDH 0003DEH 0003DFH 0003E0H0003F0H 0003F1H 0003F2H 0003F3H 0003F4H0003F8H 0003F9H 0003FAH 0003FBH 0003FCH 0003FDH 0003FEH0003FFH 000400H 000401H 000402H 000403H 000404H 000405H 000406H 000407H 000408H 000409H 00040AH Register Memory Patch function - Patch data 5 High Memory Patch function - Patch data 6 Low Memory Patch function - Patch data 6 High Memory Patch function - Patch data 7 Low Memory Patch function - Patch data 7 High Reserved Memory Control Status Register A Memory Timing Configuration Register A Low Memory Timing Configuration Register A High Reserved Flash Memory Write Control register 1 Flash Memory Write Control register 2 Flash Memory Write Control register 3 Flash Memory Write Control register 4 Flash Memory Write Control register 5 Reserved Standby Mode control register Clock select register Clock Stabilization select register Clock monitor register Clock Frequency control register Low Clock Frequency control register High PLL Control register Low PLL Control register High RC clock timer control register Main clock timer control register Sub clock timer control register SMCR CKSR CKSSR CKMR CKFCRL CKFCRH PLLCRL PLLCRH RCTCR MCTCR SCTCR PLLCR CKFCR FMWC1 FMWC2 FMWC3 FMWC4 FMWC5 MCSRA MTCRAL MTCRAH MTCRA Abbreviation 8-bit access PFDH5 PFDL6 PFDH6 PFDL7 PFDH7 PFD7 PFD6 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W
30
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (12 of 28) Address 00040BH 00040CH 00040DH 00040EH 00040FH 000410H000414H 000415H 000416H 000417H 000418H 000419H 00041AH 00041BH 00041CH00042BH 00042CH 00042DH 00042EH00042FH 000430H 000431H 000432H 000433H 000434H 000435H 000436H 000437H000443H 000444H 000445H Register Reset cause and clock status register with clear function Reset configuration register Reset cause and clock status register Watch dog timer configuration register Watch dog timer clear pattern register Reserved Clock output activation register Clock output configuration register 0 Clock output configuration register 1 Clock Modulator control register Reserved Clock Modulator Parameter register Low Clock Modulator Parameter register High Reserved Voltage Regulator Control register Clock Input and LVD Control Register Reserved I/O Port P00 - Data Direction Register I/O Port P01 - Data Direction Register I/O Port P02 - Data Direction Register I/O Port P03 - Data Direction Register I/O Port P04 - Data Direction Register I/O Port P05 - Data Direction Register I/O Port P06 - Data Direction Register Reserved I/O Port P00 - Port Input Enable Register I/O Port P01 - Port Input Enable Register PIER00 PIER01 DDR00 DDR01 DDR02 DDR03 DDR04 DDR05 DDR06 VRCR CILCR CMPRL CMPRH CMPR COAR COCR0 COCR1 CMCR Abbreviation 8-bit access RCCSRC RCR RCCSR WDTC WDTCP Abbreviation 16-bit access Access R R/W R R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FME-MB96350 rev 7
31
MB96350 Series
I/O map MB96(F)35x (13 of 28) Address 000446H 000447H 000448H 000449H 00044AH 00044BH000457H 000458H 000459H 00045AH 00045BH 00045CH 00045DH 00045EH 00045FH00046BH 00046CH 00046DH 00046EH 00046FH 000470H 000471H 000472H 000473H00047FH 000480H 000481H 000482H 000483H 000484H 000485H Register I/O Port P02 - Port Input Enable Register I/O Port P03 - Port Input Enable Register I/O Port P04 - Port Input Enable Register I/O Port P05 - Port Input Enable Register I/O Port P06 - Port Input Enable Register Reserved I/O Port P00 - Port Input Level Register I/O Port P01 - Port Input Level Register I/O Port P02 - Port Input Level Register I/O Port P03 - Port Input Level Register I/O Port P04 - Port Input Level Register I/O Port P05 - Port Input Level Register I/O Port P06 - Port Input Level Register Reserved I/O Port P00 - Extended Port Input Level Register I/O Port P01 - Extended Port Input Level Register I/O Port P02 - Extended Port Input Level Register I/O Port P03 - Extended Port Input Level Register I/O Port P04 - Extended Port Input Level Register I/O Port P05 - Extended Port Input Level Register I/O Port P06 - Extended Port Input Level Register Reserved I/O Port P00 - Port Output Drive Register I/O Port P01 - Port Output Drive Register I/O Port P02 - Port Output Drive Register I/O Port P03 - Port Output Drive Register I/O Port P04 - Port Output Drive Register I/O Port P05 - Port Output Drive Register PODR00 PODR01 PODR02 PODR03 PODR04 PODR05 EPILR00 EPILR01 EPILR02 EPILR03 EPILR04 EPILR05 EPILR06 PILR00 PILR01 PILR02 PILR03 PILR04 PILR05 PILR06 Abbreviation 8-bit access PIER02 PIER03 PIER04 PIER05 PIER06 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
32
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (14 of 28) Address 000486H 000487H0004A7H 0004A8H 0004A9H 0004AAH 0004ABH 0004ACH 0004ADH 0004AEH 0004AFH0004BBH 0004BCH 0004BDH 0004BEH 0004BFH 0004C0H 0004C1H 0004C2H 0004C3H0004CFH 0004D0H 0004D1H 0004D2H 0004D3H 0004D4H 0004D5H 0004D6H 0004D7H 0004D8H 0004D9H Register I/O Port P06 - Port Output Drive Register Reserved I/O Port P00 - Pull-Up resistor Control Register I/O Port P01 - Pull-Up resistor Control Register I/O Port P02 - Pull-Up resistor Control Register I/O Port P03 - Pull-Up resistor Control Register I/O Port P04 - Pull-Up resistor Control Register I/O Port P05 - Pull-Up resistor Control Register I/O Port P06 - Pull-Up resistor Control Register Reserved I/O Port P00 - External Pin State Register I/O Port P01 - External Pin State Register I/O Port P02 - External Pin State Register I/O Port P03 - External Pin State Register I/O Port P04 - External Pin State Register I/O Port P05 - External Pin State Register I/O Port P06 - External Pin State Register Reserved ADC analog input enable register 0 ADC analog input enable register 1 ADC analog input enable register 2 ADC analog input enable register 3 ADC analog input enable register 4 Reserved Peripheral Resource Relocation Register 0 Peripheral Resource Relocation Register 1 Peripheral Resource Relocation Register 2 Peripheral Resource Relocation Register 3 PRRR0 PRRR1 PRRR2 PRRR3 ADER0 ADER1 ADER2 ADER3 ADER4 EPSR00 EPSR01 EPSR02 EPSR03 EPSR04 EPSR05 EPSR06 PUCR00 PUCR01 PUCR02 PUCR03 PUCR04 PUCR05 PUCR06 Abbreviation 8-bit access PODR06 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W
FME-MB96350 rev 7
33
MB96350 Series
I/O map MB96(F)35x (15 of 28) Address 0004DAH 0004DBH 0004DCH 0004DDH 0004DEH 0004DFH 0004E0H 0004E1H 0004E2H 0004E3H 0004E4H 0004E5H 0004E6H 0004E7H 0004E8H 0004E9H 0004EAH 0004EBH 0004ECH 0004EDH 0004EEH 0004EFH 0004F0H 0004F1H 0004F2H0004F9H 0004FAH 0004FBH0004FFH 000500H 000501H Register Peripheral Resource Relocation Register 4 Peripheral Resource Relocation Register 5 Peripheral Resource Relocation Register 6 Peripheral Resource Relocation Register 7 Peripheral Resource Relocation Register 8 Peripheral Resource Relocation Register 9 RTC - Sub Second Register L RTC - Sub Second Register M RTC - Sub-Second Register H RTC - Second Register RTC - Minutes RTC - Hour RTC - Timer Control Extended Register RTC - Clock select register RTC - Timer Control Register Low RTC - Timer Control Register High CAL - Calibration unit Control register Reserved CAL - Duration Timer Data Register Low CAL - Duration Timer Data Register High CAL - Calibration Timer Register 2 Low CAL - Calibration Timer Register 2 High CAL - Calibration Timer Register 1 Low CAL - Calibration Timer Register 1 High Reserved RLT - Timer input select (for Cascading) Reserved FRT2 - Data register of free-running timer FRT2 - Data register of free-running timer TCDT2 TMISR CUTDL CUTDH CUTR2L CUTR2H CUTR1L CUTR1H CUTR1 CUTR2 CUTD Abbreviation 8-bit access PRRR4 PRRR5 PRRR6 PRRR7 PRRR8 PRRR9 WTBRL0 WTBRH0 WTBR1 WTSR WTMR WTHR WTCER WTCKSR WTCRL WTCRH CUCR WTCR WTBR0 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W
34
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (16 of 28) Address 000502H 000503H 000504H 000505H 000506H 000507H 000508H000513H 000514H 000515H 000516H 000517H 000518H 000519H 00051AH 00051BH 00051CH 00051DH 00051EH 00051FH 000520H00053DH 00053EH 00053FH 000540H 000540H 000541H 000542H Register FRT2 - Control status register of free-running timer Low FRT2 - Control status register of free-running timer High FRT3 - Data register of free-running timer FRT3 - Data register of free-running timer FRT3 - Control status register of free-running timer Low FRT3 - Control status register of free-running timer High Reserved ICU8/ICU9 - Control Status Register ICU8/ICU9 - Edge Register ICU8 - Capture Register Low ICU8 - Capture Register High ICU9 - Capture Register Low ICU9 - Capture Register High ICU10/ICU11 - Control Status Register ICU10/ICU11 - Edge Register ICU10 - Capture Register Low ICU10 - Capture Register High ICU11 - Capture Register Low ICU11 - Capture Register High Reserved USART7 - Serial Mode Register USART7 - Serial Control Register USART7 - Serial TX Register USART7 - Serial RX Register USART7 - Serial Status Register USART7 - Ext. Control/Com. Register SMR7 SCR7 TDR7 RDR7 SSR7 ECCR7 ICS89 ICE89 IPCPL8 IPCPH8 IPCPL9 IPCPH9 ICS1011 ICE1011 IPCPL10 IPCPH10 IPCPL11 IPCPH11 IPCP11 IPCP10 IPCP9 IPCP8 TCCSL3 TCCSH3 TCCS3 Abbreviation 8-bit access TCCSL2 TCCSH2 TCDT3 Abbreviation 16-bit access TCCS2 Access R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R R R R R/W R/W W R R/W R/W
FME-MB96350 rev 7
35
MB96350 Series
I/O map MB96(F)35x (17 of 28) Address 000543H 000544H 000545H 000546H 000547H 000548H 000549H 00054AH 00054AH 00054BH 00054CH 00054DH 00054EH 00054FH 000550H 000551H000563H 000564H 000565H 000566H 000567H 000568H 000569H 00056AH 00056BH 00056CH 00056DH 00056EH 00056FH 000570H Register USART7 - Ext. Status Com. Register USART7 - Baud Rate Generator Register Low USART7 - Baud Rate Generator Register High USART7 - Extended Serial Interrupt Register Reserved USART8 - Serial Mode Register USART8 - Serial Control Register USART8 - Serial TX Register USART8 - Serial RX Register USART8 - Serial Status Register USART8 - Ext. Control/Com. Register USART8 - Ext. Status Com. Register USART8 - Baud Rate Generator Register Low USART8 - Baud Rate Generator Register High USART8 - Extended Serial Interrupt Register Reserved PPG6 - Timer register PPG6 - Timer register PPG6 - Period setting register PPG6 - Period setting register PPG6 - Duty cycle register PPG6 - Duty cycle register PPG6 - Control status register Low PPG6 - Control status register High PPG7 - Timer register PPG7 - Timer register PPG7 - Period setting register PPG7 - Period setting register PPG7 - Duty cycle register PDUT7 PCSR7 PCNL6 PCNH6 PTMR7 PCN6 PDUT6 PCSR6 PTMR6 SMR8 SCR8 TDR8 RDR8 SSR8 ECCR8 ESCR8 BGRL8 BGRH8 ESIR8 BGR8 Abbreviation 8-bit access ESCR7 BGRL7 BGRH7 ESIR7 BGR7 Abbreviation 16-bit access Access R/W R/W R/W R/W R/W R/W W R R/W R/W R/W R/W R/W R/W R R W W W W R/W R/W R R W W W
36
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (18 of 28) Address 000571H 000572H 000573H 000574H 000575H 000576H 000577H 000578H 000579H 00057AH 00057BH 00057CH 00057DH 00057EH 00057FH 000580H 000581H 000582H 000583H 000584H 000585H 000586H 000587H 000588H 000589H 00058AH 00058BH 00058CH 00058DH 00058EH Register PPG7 - Duty cycle register PPG7 - Control status register Low PPG7 - Control status register High PPG11-PPG8 - General Control register 1 Low PPG11-PPG8 - General Control register 1 High PPG11-PPG8 - General Control register 2 Low PPG11-PPG8 - General Control register 2 High PPG8 - Timer register PPG8 - Timer register PPG8 - Period setting register PPG8 - Period setting register PPG8 - Duty cycle register PPG8 - Duty cycle register PPG8 - Control status register Low PPG8 - Control status register High PPG9 - Timer register PPG9 - Timer register PPG9 - Period setting register PPG9 - Period setting register PPG9 - Duty cycle register PPG9 - Duty cycle register PPG9 - Control status register Low PPG9 - Control status register High PPG10 - Timer register PPG10 - Timer register PPG10 - Period setting register PPG10 - Period setting register PPG10 - Duty cycle register PPG10 - Duty cycle register PPG10 - Control status register Low PCNL10 PCN10 PDUT10 PCSR10 PCNL9 PCNH9 PTMR10 PCN9 PDUT9 PCSR9 PCNL8 PCNH8 PTMR9 PCN8 PDUT8 PCSR8 PCNL7 PCNH7 GCN1L2 GCN1H2 GCN2L2 GCN2H2 PTMR8 GCN22 GCN12 PCN7 Abbreviation 8-bit access Abbreviation 16-bit access Access W R/W R/W R/W R/W R/W R/W R R W W W W R/W R/W R R W W W W R/W R/W R R W W W W R/W
FME-MB96350 rev 7
37
MB96350 Series
I/O map MB96(F)35x (19 of 28) Address 00058FH 000590H 000591H 000592H 000593H 000594H 000595H 000596H 000597H 000598H 000599H 00059AH 00059BH 00059CH 00059DH 00059EH 00059FH 0005A0H 0005A1H 0005A2H 0005A3H 0005A4H 0005A5H 0005A6H 0005A7H 0005A8H 0005A9H 0005AAH 0005ABH 0005ACH Register PPG10 - Control status register High PPG11 - Timer register PPG11 - Timer register PPG11 - Period setting register PPG11 - Period setting register PPG11 - Duty cycle register PPG11 - Duty cycle register PPG11 - Control status register Low PPG11 - Control status register High PPG15-PPG12 - General Control register 1 Low PPG15-PPG12 - General Control register 1 High PPG15-PPG12 - General Control register 2 Low PPG15-PPG12 - General Control register 2 High PPG12 - Timer register PPG12 - Timer register PPG12 - Period setting register PPG12 - Period setting register PPG12 - Duty cycle register PPG12 - Duty cycle register PPG12 - Control status register Low PPG12 - Control status register High PPG13 - Timer register PPG13 - Timer register PPG13 - Period setting register PPG13 - Period setting register PPG13 - Duty cycle register PPG13 - Duty cycle register PPG13 - Control status register Low PPG13 - Control status register High PPG14 - Timer register PCNL13 PCNH13 PTMR14 PCN13 PDUT13 PCSR13 PCNL12 PCNH12 PTMR13 PCN12 PDUT12 PCSR12 PCNL11 PCNH11 GCN1L3 GCN1H3 GCN2L3 GCN2H3 PTMR12 GCN23 GCN13 PCN11 PDUT11 PCSR11 Abbreviation 8-bit access PCNH10 PTMR11 Abbreviation 16-bit access Access R/W R R W W W W R/W R/W R/W R/W R/W R/W R R W W W W R/W R/W R R W W W W R/W R/W R
38
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (20 of 28) Address 0005ADH 0005AEH 0005AFH 0005B0H 0005B1H 0005B2H 0005B3H 0005B4H 0005B5H 0005B6H 0005B7H 0005B8H 0005B9H 0005BAH 0005BBH 0005BCH 0005BDH 0005BEH 0005BFH 0005C0H 0005C1H 0005C2H 0005C3H 0005C4H 0005C5H 0005C6H 0005C7H 0005C8H 0005C9H 0005CAH Register PPG14 - Timer register PPG14 - Period setting register PPG14 - Period setting register PPG14 - Duty cycle register PPG14 - Duty cycle register PPG14 - Control status register Low PPG14 - Control status register High PPG15 - Timer register PPG15 - Timer register PPG15 - Period setting register PPG15 - Period setting register PPG15 - Duty cycle register PPG15 - Duty cycle register PPG15 - Control status register Low PPG15 - Control status register High PPG19-PPG16 - General Control register 1 Low PPG19-PPG16 - General Control register 1 High PPG19-PPG16 - General Control register 2 Low PPG19-PPG16 - General Control register 2 High PPG16 - Timer register PPG16 - Timer register PPG16 - Period setting register PPG16 - Period setting register PPG16 - Duty cycle register PPG16 - Duty cycle register PPG16 - Control status register Low PPG16 - Control status register High PPG17 - Timer register PPG17 - Timer register PPG17 - Period setting register PCSR17 PCNL16 PCNH16 PTMR17 PCN16 PDUT16 PCSR16 PCNL15 PCNH15 GCN1L4 GCN1H4 GCN2L4 GCN2H4 PTMR16 GCN24 GCN14 PCN15 PDUT15 PCSR15 PCNL14 PCNH14 PTMR15 PCN14 PDUT14 PCSR14 Abbreviation 8-bit access Abbreviation 16-bit access Access R W W W W R/W R/W R R W W W W R/W R/W R/W R/W R/W R/W R R W W W W R/W R/W R R W
FME-MB96350 rev 7
39
MB96350 Series
I/O map MB96(F)35x (21 of 28) Address 0005CBH 0005CCH 0005CDH 0005CEH 0005CFH 0005D0H 0005D1H 0005D2H 0005D3H 0005D4H 0005D5H 0005D6H 0005D7H 0005D8H 0005D9H 0005DAH 0005DBH 0005DCH 0005DDH 0005DEH 0005DFH 0005E0H00065FH 000660H 000661H 000662H 000663H 000664H0006DFH 0006E0H 0006E1H Register PPG17 - Period setting register PPG17 - Duty cycle register PPG17 - Duty cycle register PPG17 - Control status register Low PPG17 - Control status register High PPG18 - Timer register PPG18 - Timer register PPG18 - Period setting register PPG18 - Period setting register PPG18 - Duty cycle register PPG18 - Duty cycle register PPG18 - Control status register Low PPG18 - Control status register High PPG19 - Timer register PPG19 - Timer register PPG19 - Period setting register PPG19 - Period setting register PPG19 - Duty cycle register PPG19 - Duty cycle register PPG19 - Control status register Low PPG19 - Control status register High Reserved Peripheral Resource Relocation Register 10 Peripheral Resource Relocation Register 11 Peripheral Resource Relocation Register 12 Peripheral Resource Relocation Register 13 Reserved External Bus - Area configuration register 0 Low External Bus - Area configuration register 0 High EACL0 EACH0 EAC0 PRRR10 PRRR11 PRRR12 PRRR13 PCNL19 PCNH19 PCN19 PDUT19 PCSR19 PCNL18 PCNH18 PTMR19 PCN18 PDUT18 PCSR18 PCNL17 PCNH17 PTMR18 PCN17 PDUT17 Abbreviation 8-bit access Abbreviation 16-bit access Access W W W R/W R/W R R W W W W R/W R/W R R W W W W R/W R/W R/W R/W R/W W R/W R/W
40
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (22 of 28) Address 0006E2H 0006E3H 0006E4H 0006E5H 0006E6H 0006E7H 0006E8H 0006E9H 0006EAH 0006EBH 0006ECH 0006EDH 0006EEH 0006EFH 0006F0H 0006F1H 0006F2H 0006F3H 0006F4H 0006F5H 0006F6H0007FFH 000800H 000801H 000802H 000803H 000804H 000805H 000806H 000807H Register External Bus - Area configuration register 1 Low External Bus - Area configuration register 1 High External Bus - Area configuration register 2 Low External Bus - Area configuration register 2 High External Bus - Area configuration register 3 Low External Bus - Area configuration register 3 High External Bus - Area configuration register 4 Low External Bus - Area configuration register 4 High External Bus - Area configuration register 5 Low External Bus - Area configuration register 5 High External Bus - Area select register 2 External Bus - Area select register 3 External Bus - Area select register 4 External Bus - Area select register 5 External Bus - Mode register External Bus - Clock and Function register External Bus - Address output enable register 0 External Bus - Address output enable register 1 External Bus - Address output enable register 2 External Bus - Control signal register Reserved CAN1 - Control register Low CAN1 - Control register High (reserved) CAN1 - Status register Low CAN1 - Status register High (reserved) CAN1 - Error Counter Low (Transmit) CAN1 - Error Counter High (Receive) CAN1 - Bit Timing Register Low CAN1 - Bit Timing Register High CTRLRL1 CTRLRH1 STATRL1 STATRH1 ERRCNTL1 ERRCNTH1 BTRL1 BTRH1 BTR1 ERRCNT1 STATR1 CTRLR1 Abbreviation 8-bit access EACL1 EACH1 EACL2 EACH2 EACL3 EACH3 EACL4 EACH4 EACL5 EACH5 EAS2 EAS3 EAS4 EAS5 EBM EBCF EBAE0 EBAE1 EBAE2 EBCS EAC5 EAC4 EAC3 EAC2 Abbreviation 16-bit access EAC1 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R R R/W R/W
FME-MB96350 rev 7
41
MB96350 Series
I/O map MB96(F)35x (23 of 28) Address 000808H 000809H 00080AH 00080BH 00080CH 00080DH 00080EH00080FH 000810H 000811H 000812H 000813H 000814H 000815H 000816H 000817H 000818H 000819H 00081AH 00081BH 00081CH 00081DH 00081EH 00081FH 000820H 000821H 000822H 000823H 000824H 000825H Register CAN1 - Interrupt Register Low CAN1 - Interrupt Register High CAN1 - Test Register Low CAN1 - Test Register High (reserved) CAN1 - BRP Extension register Low CAN1 - BRP Extension register High (reserved) Reserved CAN1 - IF1 Command request register Low CAN1 - IF1 Command request register High CAN1 - IF1 Command Mask register Low CAN1 - IF1 Command Mask register High (reserved) CAN1 - IF1 Mask 1 Register Low CAN1 - IF1 Mask 1 Register High CAN1 - IF1 Mask 2 Register Low CAN1 - IF1 Mask 2 Register High CAN1 - IF1 Arbitration 1 Register Low CAN1 - IF1 Arbitration 1 Register High CAN1 - IF1 Arbitration 2 Register Low CAN1 - IF1 Arbitration 2 Register High CAN1 - IF1 Message Control Register Low CAN1 - IF1 Message Control Register High CAN1 - IF1 Data A1 Low CAN1 - IF1 Data A1 High CAN1 - IF1 Data A2 Low CAN1 - IF1 Data A2 High CAN1 - IF1 Data B1 Low CAN1 - IF1 Data B1 High CAN1 - IF1 Data B2 Low CAN1 - IF1 Data B2 High IF1CREQL1 IF1CREQH1 IF1CMSKL1 IF1CMSKH1 IF1MSK1L1 IF1MSK1H1 IF1MSK2L1 IF1MSK2H1 IF1ARB1L1 IF1ARB1H1 IF1ARB2L1 IF1ARB2H1 IF1MCTRL1 IF1MCTRH1 IF1DTA1L1 IF1DTA1H1 IF1DTA2L1 IF1DTA2H1 IF1DTB1L1 IF1DTB1H1 IF1DTB2L1 IF1DTB2H1 IF1DTB21 IF1DTB11 IF1DTA21 IF1DTA11 IF1MCTR1 IF1ARB21 IF1ARB11 IF1MSK21 IF1MSK11 IF1CMSK1 IF1CREQ1 Abbreviation 8-bit access INTRL1 INTRH1 TESTRL1 TESTRH1 BRPERL1 BRPERH1 BRPER1 TESTR1 Abbreviation 16-bit access INTR1 Access R R R/W R R/W R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
42
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (24 of 28) Address 000826H00083FH 000840H 000841H 000842H 000843H 000844H 000845H 000846H 000847H 000848H 000849H 00084AH 00084BH 00084CH 00084DH 00084EH 00084FH 000850H 000851H 000852H 000853H 000854H 000855H 000856H00087FH 000880H 000881H 000882H 000883H Reserved CAN1 - IF2 Command request register Low CAN1 - IF2 Command request register High CAN1 - IF2 Command Mask register Low CAN1 - IF2 Command Mask register High (reserved) CAN1 - IF2 Mask 1 Register Low CAN1 - IF2 Mask 1 Register High CAN1 - IF2 Mask 2 Register Low CAN1 - IF2 Mask 2 Register High CAN1 - IF2 Arbitration 1 Register Low CAN1 - IF2 Arbitration 1 Register High CAN1 - IF2 Arbitration 2 Register Low CAN1 - IF2 Arbitration 2 Register High CAN1 - IF2 Message Control Register Low CAN1 - IF2 Message Control Register High CAN1 - IF2 Data A1 Low CAN1 - IF2 Data A1 High CAN1 - IF2 Data A2 Low CAN1 - IF2 Data A2 High CAN1 - IF2 Data B1 Low CAN1 - IF2 Data B1 High CAN1 - IF2 Data B2 Low CAN1 - IF2 Data B2 High Reserved CAN1 - Transmission Request 1 Register Low CAN1 - Transmission Request 1 Register High CAN1 - Transmission Request 2 Register Low CAN1 - Transmission Request 2 Register High TREQR1L1 TREQR1H1 TREQR2L1 TREQR2H1 TREQR21 TREQR11 IF2CREQL1 IF2CREQH1 IF2CMSKL1 IF2CMSKH1 IF2MSK1L1 IF2MSK1H1 IF2MSK2L1 IF2MSK2H1 IF2ARB1L1 IF2ARB1H1 IF2ARB2L1 IF2ARB2H1 IF2MCTRL1 IF2MCTRH1 IF2DTA1L1 IF2DTA1H1 IF2DTA2L1 IF2DTA2H1 IF2DTB1L1 IF2DTB1H1 IF2DTB2L1 IF2DTB2H1 IF2DTB21 IF2DTB11 IF2DTA21 IF2DTA11 IF2MCTR1 IF2ARB21 IF2ARB11 IF2MSK21 IF2MSK11 IF2CMSK1 IF2CREQ1 Register Abbreviation 8-bit access Abbreviation 16-bit access Access R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
FME-MB96350 rev 7
43
MB96350 Series
I/O map MB96(F)35x (25 of 28) Address 000884H00088FH 000890H 000891H 000892H 000893H 000894H00089FH 0008A0H 0008A1H 0008A2H 0008A3H 0008A4H0008AFH 0008B0H 0008B1H 0008B2H 0008B3H 0008B4H0008CDH 0008CEH 0008CFH0008FFH 000900H 000901H 000902H 000903H 000904H 000905H 000906H 000907H 000908H Reserved CAN1 - New Data 1 Register Low CAN1 - New Data 1 Register High CAN1 - New Data 2 Register Low CAN1 - New Data 2 Register High Reserved CAN1 - Interrupt Pending 1 Register Low CAN1 - Interrupt Pending 1 Register High CAN1 - Interrupt Pending 2 Register Low CAN1 - Interrupt Pending 2 Register High Reserved CAN1 - Message Valid 1 Register Low CAN1 - Message Valid 1 Register High CAN1 - Message Valid 2 Register Low CAN1 - Message Valid 2 Register High Reserved CAN1 - Output enable register Reserved CAN2 - Control register Low CAN2 - Control register High (reserved) CAN2 - Status register Low CAN2 - Status register High (reserved) CAN2 - Error Counter Low (Transmit) CAN2 - Error Counter High (Receive) CAN2 - Bit Timing Register Low CAN2 - Bit Timing Register High CAN2 - Interrupt Register Low CTRLRL2 CTRLRH2 STATRL2 STATRH2 ERRCNTL2 ERRCNTH2 BTRL2 BTRH2 INTRL2 INTR2 BTR2 ERRCNT2 STATR2 CTRLR2 COER1 MSGVAL1L1 MSGVAL1H1 MSGVAL2L1 MSGVAL2H1 MSGVAL21 MSGVAL11 INTPND1L1 INTPND1H1 INTPND2L1 INTPND2H1 INTPND21 INTPND11 NEWDT1L1 NEWDT1H1 NEWDT2L1 NEWDT2H1 NEWDT21 NEWDT11 Register Abbreviation 8-bit access Abbreviation 16-bit access Access R R R R R R R R R R R R R/W R/W R R/W R R R R/W R/W R
44
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (26 of 28) Address 000909H 00090AH 00090BH 00090CH 00090DH 00090EH00090FH 000910H 000911H 000912H 000913H 000914H 000915H 000916H 000917H 000918H 000919H 00091AH 00091BH 00091CH 00091DH 00091EH 00091FH 000920H 000921H 000922H 000923H 000924H 000925H Register CAN2 - Interrupt Register High CAN2 - Test Register Low CAN2 - Test Register High (reserved) CAN2 - BRP Extension register Low CAN2 - BRP Extension register High (reserved) Reserved CAN2 - IF1 Command request register Low CAN2 - IF1 Command request register High CAN2 - IF1 Command Mask register Low CAN2 - IF1 Command Mask register High (reserved) CAN2 - IF1 Mask 1 Register Low CAN2 - IF1 Mask 1 Register High CAN2 - IF1 Mask 2 Register Low CAN2 - IF1 Mask 2 Register High CAN2 - IF1 Arbitration 1 Register Low CAN2 - IF1 Arbitration 1 Register High CAN2 - IF1 Arbitration 2 Register Low CAN2 - IF1 Arbitration 2 Register High CAN2 - IF1 Message Control Register Low CAN2 - IF1 Message Control Register High CAN2 - IF1 Data A1 Low CAN2 - IF1 Data A1 High CAN2 - IF1 Data A2 Low CAN2 - IF1 Data A2 High CAN2 - IF1 Data B1 Low CAN2 - IF1 Data B1 High CAN2 - IF1 Data B2 Low CAN2 - IF1 Data B2 High IF1CREQL2 IF1CREQH2 IF1CMSKL2 IF1CMSKH2 IF1MSK1L2 IF1MSK1H2 IF1MSK2L2 IF1MSK2H2 IF1ARB1L2 IF1ARB1H2 IF1ARB2L2 IF1ARB2H2 IF1MCTRL2 IF1MCTRH2 IF1DTA1L2 IF1DTA1H2 IF1DTA2L2 IF1DTA2H2 IF1DTB1L2 IF1DTB1H2 IF1DTB2L2 IF1DTB2H2 IF1DTB22 IF1DTB12 IF1DTA22 IF1DTA12 IF1MCTR2 IF1ARB22 IF1ARB12 IF1MSK22 IF1MSK12 IF1CMSK2 IF1CREQ2 Abbreviation 8-bit access INTRH2 TESTRL2 TESTRH2 BRPERL2 BRPERH2 BRPER2 TESTR2 Abbreviation 16-bit access Access R R/W R R/W R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FME-MB96350 rev 7
45
MB96350 Series
I/O map MB96(F)35x (27 of 28) Address 000926H00093FH 000940H 000941H 000942H 000943H 000944H 000945H 000946H 000947H 000948H 000949H 00094AH 00094BH 00094CH 00094DH 00094EH 00094FH 000950H 000951H 000952H 000953H 000954H 000955H 000956H00097FH 000980H 000981H 000982H 000983H Reserved CAN2 - IF2 Command request register Low CAN2 - IF2 Command request register High CAN2 - IF2 Command Mask register Low CAN2 - IF2 Command Mask register High (reserved) CAN2 - IF2 Mask 1 Register Low CAN2 - IF2 Mask 1 Register High CAN2 - IF2 Mask 2 Register Low CAN2 - IF2 Mask 2 Register High CAN2 - IF2 Arbitration 1 Register Low CAN2 - IF2 Arbitration 1 Register High CAN2 - IF2 Arbitration 2 Register Low CAN2 - IF2 Arbitration 2 Register High CAN2 - IF2 Message Control Register Low CAN2 - IF2 Message Control Register High CAN2 - IF2 Data A1 Low CAN2 - IF2 Data A1 High CAN2 - IF2 Data A2 Low CAN2 - IF2 Data A2 High CAN2 - IF2 Data B1 Low CAN2 - IF2 Data B1 High CAN2 - IF2 Data B2 Low CAN2 - IF2 Data B2 High Reserved CAN2 - Transmission Request 1 Register Low CAN2 - Transmission Request 1 Register High CAN2 - Transmission Request 2 Register Low CAN2 - Transmission Request 2 Register High TREQR1L2 TREQR1H2 TREQR2L2 TREQR2H2 TREQR22 TREQR12 IF2CREQL2 IF2CREQH2 IF2CMSKL2 IF2CMSKH2 IF2MSK1L2 IF2MSK1H2 IF2MSK2L2 IF2MSK2H2 IF2ARB1L2 IF2ARB1H2 IF2ARB2L2 IF2ARB2H2 IF2MCTRL2 IF2MCTRH2 IF2DTA1L2 IF2DTA1H2 IF2DTA2L2 IF2DTA2H2 IF2DTB1L2 IF2DTB1H2 IF2DTB2L2 IF2DTB2H2 IF2DTB22 IF2DTB12 IF2DTA22 IF2DTA12 IF2MCTR2 IF2ARB22 IF2ARB12 IF2MSK22 IF2MSK12 IF2CMSK2 IF2CREQ2 Register Abbreviation 8-bit access Abbreviation 16-bit access Access R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R
46
FME-MB96350 rev 7
MB96350 Series
I/O map MB96(F)35x (28 of 28) Address 000984H00098FH 000990H 000991H 000992H 000993H 000994H00099FH 0009A0H 0009A1H 0009A2H 0009A3H 0009A4H0009AFH 0009B0H 0009B1H 0009B2H 0009B3H 0009B4H0009CDH 0009CEH 0009CFH000BFFH Reserved CAN2 - New Data 1 Register Low CAN2 - New Data 1 Register High CAN2 - New Data 2 Register Low CAN2 - New Data 2 Register High Reserved CAN2 - Interrupt Pending 1 Register Low CAN2 - Interrupt Pending 1 Register High CAN2 - Interrupt Pending 2 Register Low CAN2 - Interrupt Pending 2 Register High Reserved CAN2 - Message Valid 1 Register Low CAN2 - Message Valid 1 Register High CAN2 - Message Valid 2 Register Low CAN2 - Message Valid 2 Register High Reserved CAN2 - Output enable register Reserved COER2 MSGVAL1L2 MSGVAL1H2 MSGVAL2L2 MSGVAL2H2 MSGVAL22 MSGVAL12 INTPND1L2 INTPND1H2 INTPND2L2 INTPND2H2 INTPND22 INTPND12 NEWDT1L2 NEWDT1H2 NEWDT2L2 NEWDT2H2 NEWDT22 NEWDT12 Register Abbreviation 8-bit access Abbreviation 16-bit access Access R R R R R R R R R R R R R/W -
Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved address results in reading `X'. Registers of resources which are described in this table, but which are not supported by the device, should also be handled as "Reserved".
FME-MB96350 rev 7
47
MB96350 Series
INTERRUPT VECTOR TABLE
Interrupt vector table MB96(F)35x (1 of 3) Offset in Index in Vector Cleared by vector taVector name ICR to pronumber DMA ble gram 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH EXTINT7 EXTINT8 EXTINT9 EXTINT10 EXTINT11 EXTINT12 EXTINT13 EXTINT14 EXTINT15 CAN1 Yes Yes Yes Yes Yes Yes Yes Yes Yes No 23 24 25 26 27 28 29 30 31 32 EXTINT2 EXTINT3 EXTINT4 Yes Yes Yes 19 20 21 CALLV0 CALLV1 CALLV2 CALLV3 CALLV4 CALLV5 CALLV6 CALLV7 RESET INT9 EXCEPTION NMI DLY RC_TIMER MC_TIMER SC_TIMER PLL_UNLOCK EXTINT0 No No No No No No No No No No No No No No No No No Yes 12 13 14 15 16 17 Non-Maskable Interrupt Delayed Interrupt RC Timer Main Clock Timer Sub Clock Timer Reserved External Interrupt 0 Reserved External Interrupt 2 External Interrupt 3 External Interrupt 4 Reserved External Interrupt 7 External Interrupt 8 External Interrupt 9 External Interrupt 10 External Interrupt 11 External Interrupt 12 External Interrupt 13 External Interrupt 14 External Interrupt 15 CAN Controller 1 (only MB96F356Y/R)
Description
48
FME-MB96350 rev 7
MB96350 Series
Interrupt vector table MB96(F)35x (2 of 3) Offset in Index in Vector Cleared by vector taVector name ICR to pronumber DMA ble gram 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 378H 374H 370H 36CH 368H 364H 360 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H ICU4 ICU5 ICU6 ICU7 Yes Yes Yes Yes 63 64 65 66 CAN2 PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 PPG6 PPG7 PPG8 PPG9 PPG10 PPG11 PPG12 PPG13 PPG14 PPG15 PPG16 PPG17 PPG18 PPG19 RLT0 RLT1 RLT2 RLT3 PPGRLT ICU0 ICU1 No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Description CAN Controller 2 (only MB96F356Y/R and MB96F353R/F355R) Programmable Pulse Generator 0 Programmable Pulse Generator 1 Programmable Pulse Generator 2 Programmable Pulse Generator 3 Programmable Pulse Generator 4 Programmable Pulse Generator 5 Programmable Pulse Generator 6 Programmable Pulse Generator 7 Programmable Pulse Generator 8 Programmable Pulse Generator 9 Programmable Pulse Generator 10 Programmable Pulse Generator 11 Programmable Pulse Generator 12 Programmable Pulse Generator 13 Programmable Pulse Generator 14 Programmable Pulse Generator 15 Programmable Pulse Generator 16 Programmable Pulse Generator 17 Programmable Pulse Generator 18 Programmable Pulse Generator 19 Reload Timer 0 Reload Timer 1 Reload Timer 2 Reload Timer 3 Reload Timer 6 - dedicated for PPG Input Capture Unit 0 Input Capture Unit 1 Reserved Reserved Input Capture Unit 4 Input Capture Unit 5 Input Capture Unit 6 Input Capture Unit 7
FME-MB96350 rev 7
49
MB96350 Series
Interrupt vector table MB96(F)35x (3 of 3) Offset in Index in Vector Cleared by vector taVector name ICR to pronumber DMA ble gram 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH 2B8H 2B4H 2B0H 2ACH 2A8H 2A4H 2A0H 29CH 298H 294H 290H 28CH 288H FRT0 FRT1 FRT2 FRT3 RTC0 CAL0 IIC0 ADC0 LINR2 LINT2 LINR3 LINT3 LINR7 LINT7 LINR8 LINT8 FLASH_A Yes Yes Yes Yes No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 OCU4 OCU5 OCU6 OCU7 Yes Yes Yes Yes 71 72 73 74 ICU9 ICU10 Yes Yes 68 69 Reserved Input Capture Unit 9 Input Capture Unit 10 Reserved Output Compare Unit 4 Output Compare Unit 5 Output Compare Unit 6 Output Compare Unit 7 Reserved Reserved Free Running Timer 0 Free Running Timer 1 Free Running Timer 2 Free Running Timer 3 Real Timer Clock Clock Calibration Unit I2C interface A/D Converter LIN USART 2 RX LIN USART 2 TX LIN USART 3 RX LIN USART 3 TX LIN USART 7 RX LIN USART 7 TX LIN USART 8 RX LIN USART 8 TX Flash memory A (only Flash devices)
Description
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HANDLING DEVICES Special care is required for the following when handling the device:
* * * * * * * * * * * * Latch-up prevention Unused pins handling External clock usage Unused sub clock signal Notes on PLL clock mode operation Power supply pins (VCC/VSS) Crystal oscillator circuit Turn on sequence of power supply to A/D converter and analog inputs Pin handling when not using the A/D converter Notes on energization Stabilization of power supply voltage Serial communication
1. Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions: * A voltage higher than VCC or lower than VSS is applied to an input or output pin. * A voltage higher than the rated voltage is applied between VCC pins and VSS pins. Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
2. Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register PIER = 0). Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up, those resistors should be more than 2 k. Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above.
3. External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration. See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as follows: 1. Single phase external clock * When using a single phase external clock, X0 (X0A) pin must be driven and X1 (X1A) pin left open.
X0 X1
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2. Opposite phase external clock * When using an opposite phase external clock, X1 (X1A) must be supplied with a clock signal which has the opposite phase to the X0 (X0A) pins.
X0 X1
4. Unused sub clock signal
If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A pin and the X1A pin must be left open.
5. Notes on PLL clock mode operation
If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed.
6. Power supply pins (VCC/VSS)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range. VCC and VSS must be connected to the device from the power supply with lowest possible impedance. As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 F between VCC and VSS as close as possible to VCC and VSS pins.
7. Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area for stabilizing the operation. It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer, especially when using low-Q resonators at higher frequencies.
8. Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital power supply (VCC) on. It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously on or off is acceptable).
9. Pin handling when not using the A/D converter
It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.
10. Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50s from 0.2 V to 2.7 V.
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11. Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage, a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the transient fluctuation rate becomes 0.1V/s or less in instantaneous fluctuation for power supply switching.
12. Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit the data if an error occurs.
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ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage AD Converter voltage references Input voltage Output voltage Maximum Clamp Current Total Maximum Clamp Current "L" level maximum output current "L" level average output current "L" level maximum overall output current "L" level average overall output current "H" level maximum output current "H" level average output current "H" level maximum overall output current "H" level average overall output current Symbol VCC AVCC AVRH, AVRL VI VO ICLAMP |ICLAMP| IOL1 IOLAV1 IOL1 IOLAV1 IOH1 IOHAV1 IOH1 IOHAV1 Rating Min Max VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 -4.0 Permitted Power dissipation (Flash devices) *4 PD 0 Operating ambient temperature TA -40 -40 Storage temperature TSTG -55 400*5 560*5 +70 +105 +125 +150
o o
Unit V V V V V mA mA
Remarks
VCC = AVCC *1 AVCC AVRH, AVCC AVRL, AVRH > AVRL, AVRL AVSS VI VCC + 0.3V
*2
VO VCC + 0.3V *2 Applicable to general purpose I/O pins *3 Applicable to general purpose I/O pins *3
+4.0 40 15 5 100 50 -15 -5 -100 -50 320*5 640*5 800*5
mA Normal outputs with driving strength set to 5mA mA Normal outputs with driving strength set to 5mA mA Normal outputs mA Normal outputs mA Normal outputs with driving strength set to 5mA
mA Normal outputs with driving strength set to 5mA mA Normal outputs mA Normal outputs mW TA=105oC mW TA=85oC mW TA=75oC mW mW TA=125oC, no Flash program/ erase *6 TA=115oC, no Flash program/ erase *6 MB96V300B C
*6
C
*1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC neither when the power is switched on.
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*2: VI and VO should not exceed VCC + 0.3 V. VI should also not exceed the specified ratings. However if the maximum current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output voltages of standard ports depend on VCC. *3: * Applicable to all general purpose I/O pins (Pnn_m) * Use within recommended operating conditions. * Use at DC voltage (current) * The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode). * Sample recommended circuits: Protective Diode
VCC
Limiting resistance +B input (0V to 16V)
P-ch
N-ch
R
*4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the PCB. The actual power dissipation depends on the customer application and can be calculated as follows: PD = PIO + PINT PIO = (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports) PINT = VCC * (ICC + IA) (internal power dissipation) ICC is the total core current consumption into VCC as described in the "DC characteristics" and depends on the selected operation mode and clock frequency and the usage of functions like Flash programming or the clock modulator. IA is the analog current consumption into AVCC. *5: Worst case value for a package mounted on single layer PCB at specified TA without air flow. *6: Please contact Fujitsu for reliability limitations when using under these conditions. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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2. Recommended Operating Conditions
Value Min 3.0 3.5 Typ 4.7 Max 5.5 15
Parameter Power supply voltage Smoothing capacitor at C pin
Symbol VCC CS
Unit V F
Remarks
Use a X7R ceramic capacitor or a capacitor that has similar frequency characteristics
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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3. DC characteristics
(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Input H voltage Symbol Pin Condition CMOS Hysteresis 0.8/0.2 input selected CMOS Hysteresis Port inputs 0.7/0.3 input selected Pnn_m AUTOMOTIVE Hysteresis input selected TTL input selected VIHX0F VIHX0S VIHR VIHM Input L voltage X0 X0,X1, X0A,X1A RSTX MD2-MD0 External clock in "Fast Clock Input mode" External clock in "oscillation mode" CMOS Hysteresis 0.8/0.2 input selected CMOS Hysteresis 0.7/0.3 input sePort inputs lected Pnn_m AUTOMOTIVE Hysteresis input selected TTL input selected VILX0F VILX0S VILR VILM X0 X0,X1, X0A,X1A RSTX MD2-MD0 External clock in "Fast Clock Input mode" External clock in "oscillation mode" Value Min
0.8 VCC 0.7 VCC 0.74 VCC 0.8 VCC 2.0 0.8 VCC 2.5 0.8 VCC VCC 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3
Typ
-
Max
VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.2 VCC 0.3 VCC 0.5 VCC 0.46 VCC 0.8
Unit
Remarks
V V V V V V V V V V CMOS Hysteresis input VCC 4.5V VCC < 4.5V
-
VIH
-
-
-
-
-
-
V V VCC 4.5V VCC < 4.5V V V V V V CMOS Hysteresis input
VIL
-
-
0.2 VCC
-
0.4 0.2 VCC VSS + 0.3
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(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Output H voltage VOH2 Normal outputs Symbol Pin Condition
4.5V VCC 5.5V IOH = -2mA 3.0V VCC < 4.5V IOH = -1.6mA 4.5V VCC 5.5V VCC 0.5 -
Value Min Typ Max
Unit
Remarks
V
Driving strength set to 2mA (PODR:OD=1)
VOH5
Normal outputs
IOH = -5mA 3.0V VCC < 4.5V IOH = -3mA 4.5V VCC 5.5V
VCC 0.5
-
-
V
Driving strength set to 5mA (PODR:OD=0)
VOH3
3mA outputs
IOH = -3mA 3.0V VCC < 4.5V IOH = -2mA 4.5V VCC 5.5V
VCC 0.5
-
-
V
I/O circuit type "N"
Output L voltage VOL2 Normal outputs
IOL = +2mA 3.0V VCC < 4.5V IOL = +1.6mA 4.5V VCC 5.5V
-
-
0.4
V
Driving strength set to 2mA (PODR:OD=1)
VOL5
Normal outputs
IOL = +5mA 3.0V VCC < 4.5V IOL = +3mA 3.0V VCC 5.5V IOL = +3mA
-
-
0.4
V
Driving strength set to 5mA (PODR:OD=0)
VOL3
3mA outputs Pnn_m Pnn_m, RSTX
-
-
0.4
V
I/O circuit type "N"
VSS < VI < VCC Input leak current IIL AVSS, AVRL < VI < AVCC, AVRH VCC = 3.3V 10% VCC = 5.0V 10%
-1 40 25 100 50 +1 160 100
A Single port pin k k
Pull-up resistance
RUP
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FME-MB96350 rev 7
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(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Condition (at TA) PLL Run mode with CLKS1/2 = CLKB = CLKP1 = 16MHz, CLKP2 = 8MHz 1 Flash/ROM wait state (CLKRC and CLKSC stopped) PLL Run mode with CLKS1/2 = CLKB = CLKP1 = 32MHz, CLKP2 = 16MHz 2 Flash/ROM wait states (CLKRC and CLKSC stopped) PLL Run mode with CLKS1/2 = 48MHz, CLKB = CLKP1/2 = 24MHz ICCPLL 0 Flash/ROM wait states (CLKRC and CLKSC stopped) PLL Run mode with CLKS1/2 = CLKB = CLKP1= 56MHz, CLKP2 = 28MHz 2 Flash/ROM wait states (CLKRC and CLKSC stopped. Core voltage at 1.9V) PLL Run mode with CLKS1/2 = 96MHz, CLKB = CLKP1= 48MHz, CLKP2 = 24MHz 1 Flash/ROM wait state (CLKRC and CLKSC stopped. Core voltage at 1.9V) +25C +125C +25C +125C +25C +125C +25C +125C +25C +125C +25C +125C +25C +125C +25C +125C +25C +125C +25C +125C Value Typ 14.5 16 15 16.5 23 25 24 26 26 28 28 30 40 42 41 43 43 45 44 46 Max 19.5 mA MB96F353/F355 23 20 mA MB96F356 23.5 29 mA MB96F353/F355 33 30 mA MB96F356 34 38 mA MB96F353/F355 42 40 mA MB96F356 44 51 mA MB96F353/F355 55 52 mA MB96F356 56 56 mA MB96F353/F355 60 58 mA MB96F356 62 Unit Remarks
Power supply current in Run modes*
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(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Condition (at TA) Main Run mode with CLKS1/2 = CLKB = CLKP1/2 = 4MHz ICCMAIN 1 Flash/ROM wait state (CLKPLL, CLKSC and CLKRC stopped) RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 2MHz ICCRCH 1 Flash/ROM wait state (CLKMC, CLKPLL and CLKSC stopped) RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100kHz, SMCR:LPMS = 0 1 Flash/ROM wait state Power supply current in Run modes* ICCRCL (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) RC Run mode with CLKS1/2 = CLKB = CLKP1/2 = 100kHz, SMCR:LPMS = 1 1 Flash/ROM wait state (CLKMC, CLKPLL and +125C CLKSC stopped. Voltage regulator in low power mode, no Flash programming/erasing allowed) Sub Run mode with CLKS1/2 = CLKB = CLKP1/2 = 32kHz ICCSUB 1 Flash/ROM wait state (CLKMC, CLKPLL and +125C CLKRC stopped, no Flash programming/erasing allowed) 0.65 3 +25C 0.7 3.05 +25C +125C +25C +125C +25C +125C +25C +125C +25C +125C +25C Value Typ 4 4.7 4.2 4.9 2.5 3.2 2.7 3.4 0.18 0.73 0.4 Max 5 mA MB96F353/F355 8 5.2 mA MB96F356 8.2 3.5 mA MB96F353/F355 6.5 3.7 mA MB96F356 6.7 0.3 mA MB96F353/F355 3.1 0.6 mA MB96F356 +125C 0.95 3.4 Unit Remarks
+25C
0.15
0.25
mA
MB96F353/F355/ F356
0.1
0.2
mA
MB96F353/F355/ F356
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(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Condition (at TA) PLL Sleep mode with CLKS1/2 = CLKP1 = 16MHz, CLKP2 = 8MHz (CLKRC and CLKSC stopped) PLL Sleep mode with CLKS1/2 = CLKP1 = 32MHz, CLKP2 = 16MHz (CLKRC and CLKSC stopped) PLL Sleep mode with CLKS1/2 = 48MHz, CLKP1/2 = 24MHz (CLKRC and CLKSC stopped) PLL Sleep mode with CLKS1/2 = CLKP1= 56MHz, CLKP2 = 28MHz Power supply current in Sleep modes* (CLKRC and CLKSC stopped. Core voltage at 1.9V) PLL Sleep mode with CLKS1/2 = 96MHz, CLKP1= 48MHz, CLKP2 = 24MHz (CLKRC and CLKSC stopped. Core voltage at 1.9V) Main Sleep mode with CLKS1/2 = CLKP1/2 = 4MHz (CLKPLL, CLKSC and CLKRC stopped) +25C Value Typ 4 Max 6 mA +125C 4.7 9 MB96F353/F355/ F356 Unit Remarks
+25C
7
9.5 mA MB96F353/F355/ F356
+125C
8
12.5
+25C +125C +25C
7 8 11
9 mA 12 14.5 mA MB96F353/F355/ F356 MB96F353/F355/ F356
ICCSPLL
+125C
12
17.5
+25C
12
15 mA MB96F353/F355/ F356
+125C
13
18
+25C +125C +25C +125C +25C +125C +25C +125C
1 1.6 1.3 1.9 0.55 1.15 0.8 1.4
1.3 mA MB96F353/F355 4.1 1.8 mA MB96F356 4.6 1.1 mA MB96F353/F355 3.9 1.4 mA MB96F356 4.2
ICCSMAIN
ICCSRCH
RC Sleep mode with CLKS1/2 = CLKP1/2 = 2MHz (CLKMC, CLKPLL and CLKSC stopped)
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(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Condition (at TA) RC Sleep mode with CLKS1/2 = CLKP1/2 = 100kHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) RC Sleep mode with CLKS1/2 = CLKP1/2 = 100kHz, SMCR:LPMSS = 1 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) Sub Sleep mode with CLKS1/2 = CLKP1/2 = 32kHz (CLKMC, CLKPLL and CLKRC stopped) +25C +125C +25C +125C +25C Value Typ 0.08 0.59 0.3 0.8 0.05 Max 0.2 mA MB96F353/F355 2.95 0.5 mA MB96F356 3.3 0.15 MB96F353/F355/ F356 Unit Remarks
ICCSRCL Power supply current in Sleep modes*
mA +125C 0.56 2.9
+25C +125C
0.04 0.54 1.3 1.9 1.5 2.1 0.11 0.63 0.35 0.85 0.08
0.12 mA 2.9 1.8 mA MB96F353/F355 4.8 2 mA MB96F356 5 0.2 mA MB96F353/F355 3 0.5 mA MB96F356 3.3 0.15 mA MB96F353/F355/ F356 MB96F353/F355/ F356
ICCSSUB
ICCTPLL
+25C PLL Timer mode with CLKMC = 4MHz, CLKPLL +125C = 48MHz +25C (CLKRC and CLKSC stopped) +125C Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 0 (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in high power mode) Main Timer mode with CLKMC = 4MHz, SMCR:LPMSS = 1 (CLKPLL, CLKRC and CLKSC stopped. Voltage regulator in low power mode) +25C +125C +25C +125C +25C
Power supply current in Timer modes*
ICCTMAIN
+125C
0.6
2.9
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(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Condition (at TA) RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) RC Timer mode with CLKRC = 2MHz, SMCR:LPMSS = 1 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) Power supply current in Timer modes* RC Timer mode with CLKRC = 100kHz, SMCR:LPMSS = 0 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in high power mode) RC Timer mode with CLKRC = 100kHz, SMCR:LPMSS = 1 (CLKMC, CLKPLL and CLKSC stopped. Voltage regulator in low power mode) Sub Timer mode with CLKSC = 32kHz (CLKMC, CLKPLL and CLKRC stopped) VRCR:LPMB[2:0] = 110B Power supply current in Stop Mode (Core voltage at 1.8V) ICCH VRCR:LPMB[2:0] = 000B (Core voltage at 1.2V) +25C +125C +25C Power supply current for active Low Voltage detector Low voltage detector enabled (RCR:LVDE = 1) +125C +25C +125C 0.015 0.4 5 7 90 100 0.06 mA 2.3 10 20 140 A 150 A A MB96F353/F355/ F356 MB96F353/F355 Must be added to all current above MB96F356 Must be added to all current above 63 +25C +125C +25C +125C +25C Value Typ 0.1 0.63 0.35 0.85 0.07 Max 0.2 mA MB96F353/F355 3 0.5 mA MB96F356 3.3 0.15 mA +125C 0.6 2.9 MB96F353/F355/ F356 Unit Remarks
ICCTRCH
+25C +125C +25C +125C +25C
0.06 0.56 0.3 0.8 0.03
0.15 mA MB96F353/F355 2.95 0.45 mA MB96F356 3.2 0.1 mA MB96F353/F355/ F356
ICCTRCL
+125C
0.53
2.85
+25C +125C +25C +125C
0.035 0.53 0.02 0.52
0.1 mA 2.85 0.08 mA 2.8 MB96F353/F355/ F356
ICCTSUB
MB96F353/F355/ F356
ICCLVD
FME-MB96350 rev 7
MB96350 Series
(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Power supply current for active Clock modulator Flash Write/Erase current Input capacitance Symbol Condition (at TA) Clock modulator enabled (CMCR:PDX = 1) Current for one Flash module Value Typ 3 15 5 Max 4.5 40 15 Unit mA mA pF Remarks Must be added to all current above Must be added to all current above Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS
ICCCLOMO ICCFLASH CIN
* The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock connected to the Sub oscillator. See chapter "Standby mode and voltage regulator control circuit" of the Hardware Manual for further details about voltage regulator control.
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4. AC Characteristics Source Clock timing
(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Value Min 3 Clock frequency fC X0, X1 0 3.5 0 Clock frequency fFCI X0 3.5 32 X0A, X1A Clock frequency fCL X0A 0 0 50 Clock frequency fCR 1 RC clock stabilization time PLL Clock frequency PLL Phase Jitter Input clock pulse width Input clock pulse width 2 4 MHz 32.768 100 56 100 100 50 200 MHz Typ Max 16 16 16 56 Unit Remarks
MHz When using a crystal oscillator, PLL off MHz MHz MHz When using an opposite phase external clock, PLL off When using a crystal oscillator or opposite phase external clock, PLL on When using a single phase external clock in "Fast Clock Input mode" , PLL off When using a single phase external clock in "Fast Clock Input mode" , PLL on When using an opposite phase external clock When using a single phase external clock When using slow frequency of RC oscillator When using fast frequency of RC oscillator Applied after any reset and when activating the RC oscillator. MB96F356: 64 cycles others: 256 cycles Permitted VCO output frequency of PLL (CLKVCO) For CLKMC (PLL input clock) 4MHz, jitter coming from external oscillator, crystal or resonator is not covered Duty ratio is about 30% to 70%
kHz When using an oscillation circuit kHz kHz kHz
tRCSTAB
-
64 or 256 RC clock cycles
fCLKVCO TPSKEW PWH, PWL
X0,X1
64 8 5
-
200 5 -
MHz ns ns s
PWHL, PWLL X0A,X1A
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tCYL VIH X0 PWH PWL VIL
tCYLL VIH X0A PWHL PWLL VIL
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Internal Clock timing
(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Core Voltage Settings Parameter Internal System clock frequency (CLKS1 and CLKS2) Internal CPU clock frequency (CLKB), internal peripheral clock frequency (CLKP1) Internal peripheral clock frequency (CLKP2) Symbol Min fCLKS1, fCLKS2 0 0 fCLKB, fCLKP1 0 1.8V Max 92 88 52 Min 0 0 0 1.9V Max 96 96 56 MHz MHz MHz Others than below MB96F356 Unit Remarks
fCLKP2
0
28
0
32
MHz
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External Reset timing
(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Reset input time Symbol tRSTL Pin RSTX Value Min 500 Typ Max Unit ns Remarks
tRSTL RSTX
0.2 VCC
0.2 VCC
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MB96350 Series
Power On Reset timing
(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Power on rise time Power off time Symbol tR tOFF Pin Vcc Vcc Value Min 0.05 1 Typ Max 30 Unit ms ms Remarks
tR
VCC
0.2 V
2.7V 0.2 V tOFF 0.2 V
If the power supply is changed too rapidly, a power-on reset may occur. We recommend a smooth startup by restraining voltages when changing the power supply voltage during operation, as shown in the figure below.
VCC
3V Rising edge of 50 mV/ms maximum is allowed
FME-MB96350 rev 7
69
MB96350 Series
External Input timing
(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin INTn(_R) NMI(_R) Pnn_m Input pulse width tINH tINL TINn(_R) TTGn(_R) ADTG(_R) FRCKn(_R) INn(_R) Note : Relocated Resource Inputs have same characteristics 2*tCLKP1 + 200
(tCLKP1=1/ fCLKP1)
Condition
Value Min 200 Max
Unit ns
Used Pin input function External Interrupt NMI General Purpose IO Reload Timer PPG Trigger input
ns
AD Converter Trigger Free Running Timer external clock Input Capture
External Pin input
VIH
VIH VIL tINH tINL VIL
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FME-MB96350 rev 7
MB96350 Series
External Bus timing
Note: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing described in the different tables must then be increased by 10ns.
Basic Timing
Parameter
(TA = -40 C to +125 C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Symbol tCYC Pin Condition Value Min 25 ECLK tCYC/2-5 tCYC/2-5 -20 CSn, UBX, LBX, ECLK -20 -20 -20 -10 ALE, ECLK -10 -10 -10 A[23:16], ECLK AD[15:0], ECLK RDX, WRX, WRLX,WRHX, ECLK -15 -15 -15 -15 -10 -10 -10 -10 Max tCYC/2+5 tCYC/2+5 20 20 20 20 10 10 10 10 15 15 15 15 10 10 10 10 ns ns ns ns ns ns Unit Remarks
ECLK
tCHCL tCLCH tCHCBH
ECLK UBX/ LBX / CSn time
tCHCBL tCLCBH tCLCBL tCHLH tCHLL tCLLH tCLLL tCHAV
ECLK ALE time
ECLK address valid time
tCLAV tCLADV tCHADV tCHRWH
ECLK RDX /WRX time
tCHRWL tCLRWH tCLRWL
FME-MB96350 rev 7
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MB96350 Series
(TA = -40 C to +125 C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol tCYC ECLK tCHCL tCLCH tCHCBH ECLK UBX/ LBX / CSn time tCHCBL tCLCBH tCLCBL tCHLH ECLK ALE time tCHLL tCLLH tCLLL tCHAV ECLK address valid time tCLAV tCLADV tCHADV tCHRWH ECLK RDX /WRX time tCHRWL tCLRWH tCLRWL RDX, WRX, WRLX, WRHX, ECLK A[23:16], ECLK AD[15:0], ECLK ALE, ECLK CSn, UBX, LBX, ECLK ECLK Pin Condition Value Min 30 tCYC/2-8 tCYC/2-8 -25 -25 -25 -25 -15 -15 -15 -15 -20 -20 -20 -20 -15 -15 -15 -15 Max tCYC/2+8 tCYC/2+8 25 25 25 25 15 15 15 15 20 20 20 20 15 15 15 15 ns ns ns ns ns ns Unit Remarks
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FME-MB96350 rev 7
MB96350 Series
tCYC tCHCL ECLK 0.8*Vcc 0.2*Vcc tCHAV A[23:16] tCLAV tCLCH
tCHCBL CSn LBX UBX
tCLCBH
tCLCBL
tCHCBH
tCHRWL RDX WRX (WRLX, WRHX)
tCLRWH
tCLRWL
tCHRWH
tCLLH ALE
tCHLL
tCHLH
tCLLL
tCLADV Address
tCHADV
AD[15:0]
Refer to the Hardware Manual for detailed Timing Charts
FME-MB96350 rev 7
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MB96350 Series
Bus Timing (Read)
Parameter (TA = -40 C to +125 C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Symbol Pin Conditions
EACL:STS=0 and EACL:ACE=0
Value Min tCYC/2 - 5 tCYC - 5 3tCYC/2 - 5 tCYC - 15 Max
Unit
Remarks
ALE pulse width
tLHLL ALE
EACL:STS=1 EACL:STS=0 and EACL:ACE=1 EACL:STS=0 and EACL:ACE=0
ns
tAVLL ALE, A[23:16],
EACL:STS=1 and 3tCYC/2 - 15 EACL:ACE=0 EACL:STS=0 and EACL:ACE=1
ns ns ns ns 3tCYC - 55 ns 4tCYC - 55 5tCYC/2 - 55 ns 7tCYC/2 - 55 ns
w/o cycle extension
2tCYC - 15
Valid address ALE time
EACL:STS=1 and 5tCYC/2 - 15 EACL:ACE=1 EACL:STS=0 and EACL:ACE=0 EACL:STS=1 and EACL:ACE=0
tCYC/2 - 15 tCYC - 15
tADVLL ALE,AD[15:0]
EACL:STS=0 and 3tCYC/2 - 15 EACL:ACE=1 EACL:STS=1 and EACL:ACE=1
2tCYC - 15 tCYC/2 - 15 -15 3tCYC/2 - 15 5tCYC/2 - 15 tCYC - 15 2tCYC - 15 3 tCYC/2 - 5 0
ALE Address valid time
EACL:STS=0
tLLAX ALE, AD[15:0]
EACL:STS=1 EACL:ACE=0
ns
tAVRL Valid address RDX time
RDX, A[23:16]
EACL:ACE=1 EACL:ACE=0
tADVRL RDX, AD[15:0]
EACL:ACE=1 EACL:ACE=0
Valid address Valid data input
A[23:16], tAVDV AD[15:0]
EACL:ACE=1 EACL:ACE=0
tADVDV AD[15:0]
EACL:ACE=1
w/o cycle extension
RDX pulse width RDX Valid data input RDX Data hold time 74
tRLRH RDX tRLDV RDX, AD[15:0] tRHDX RDX, AD[15:0]

w/o cycle extension w/o cycle extension
3 tCYC/2 - 50 ns ns
FME-MB96350 rev 7
MB96350 Series
(TA = -40 C to +125 C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Address valid Data hold time RDX ALE time Symbol tAXDX Pin A[23:16], AD[15:0] Conditions Value Min 0 Max ns tCYC - 50 ns ns ns ns Unit ns
Remarks
tRHLH RDX, ALE tAVCH A[23:16], ECLK tADVCH AD[15:0], ECLK tRLCH RDX, ECLK tLLRL ALE, RDX tCHDV AD[15:0], ECLK
EACL:STS=1 and 3tCYC/2 - 10 EACL:ACE=1 other ECL:STS, tCYC/2 - 10 EACL:ACE setting
Valid address ECLK time RDX ECLK time ALE RDX time ECLK Valid data input

EACL:STS=0 EACL:STS=1
tCYC - 15 tCYC/2 - 15 tCYC/2 - 10 tCYC/2 - 10 - 10
(TA = -40 C to +125 C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Conditions
EACL:STS=0 and EACL:ACE=0
Value Min tCYC/2 - 8 tCYC - 8 3tCYC/2 - 8 tCYC - 20 Max
Unit
Remarks
ALE pulse width
tLHLL ALE
EACL:STS=1 EACL:STS=0 and EACL:ACE=1 EACL:STS=0 and EACL:ACE=0
ns
tAVLL ALE, A[23:16],
EACL:STS=1 and 3tCYC/2 - 20 EACL:ACE=0 EACL:STS=0 and EACL:ACE=1
ns ns ns
2tCYC - 20
Valid address ALE time
EACL:STS=1 and 5tCYC/2 - 20 EACL:ACE=1 EACL:STS=0 and EACL:ACE=0 EACL:STS=1 and EACL:ACE=0
tCYC/2 - 20 tCYC - 20
tADVLL ALE, AD[15:0]
EACL:STS=0 and 3tCYC/2 - 20 EACL:ACE=1 EACL:STS=1 and EACL:ACE=1
2tCYC - 20 tCYC/2 - 20 -20
ALE Address valid time
EACL:STS=0
tLLAX ALE, AD[15:0]
EACL:STS=1
FME-MB96350 rev 7
75
MB96350 Series
(TA = -40 C to +125 C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Conditions
EACL:ACE=0
Value Min 3tCYC/2 - 20 5tCYC/2 - 20 tCYC - 20 2tCYC - 20 3tCYC/2 - 8 0 0 Max
Unit
Remarks
tAVRL Valid address RDX time
RDX, A[23:16]
EACL:ACE=1 EACL:ACE=0
ns ns 3tCYC - 60 ns 4tCYC - 60 5tCYC/2 - 60 ns 7tCYC/2 - 60 ns
w/o cycle extension
tADVRL RDX, AD[15:0]
EACL:ACE=1 EACL:ACE=0
Valid address Valid data input
A[23:16], tAVDV AD[15:0]
EACL:ACE=1 EACL:ACE=0
tADVDV AD[15:0]
EACL:ACE=1
w/o cycle extension
RDX pulse width RDX Valid data input RDX Data hold time Address valid Data hold time RDX ALE time
tRLRH RDX tRLDV RDX, AD[15:0] tRHDX RDX, AD[15:0] tAXDX A[23:16]

w/o cycle extension w/o cycle extension
3tCYC/2 - 55 ns ns tCYC - 55 ns ns ns ns ns ns
tRHLH RDX, ALE tAVCH A[23:16], ECLK tADVCH AD[15:0], ECLK tRLCH RDX, ECLK tLLRL ALE, RDX tCHDV AD[15:0], ECLK
EACL:STS=1 and 3tCYC/2 - 15 EACL:ACE=1 other ECL:STS, tCYC/2 - 15 EACL:ACE setting
Valid address ECLK time RDX ECLK time ALE RDX time ECLK Valid data input

EACL:STS=0 EACL:STS=1
tCYC - 20 tCYC/2 - 20 tCYC/2 - 15 tCYC/2 - 15 - 15
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FME-MB96350 rev 7
MB96350 Series
tAVCH tADVCH ECLK 0.8*Vcc
tRLCH
tCHDV
tAVLL tADVLL ALE tLHLL tAVRL tADVRL RDX
tLLAX
tRHLH
0.2*VCC
tRLRH
tLLRL
A[23:16] tRLDV tAVDV tADVDV AD[15:0] Address VIH VIL Read data tRHDX VIH VIL tAXDX
Refer to the Hardware Manual for detailed Timing Charts .
Bus Timing (Write)
Parameter
(TA = -40 C to +125 C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Pin WRX, WRLX, WRHX, A[23:16] WRX, WRLX, WRHX, AD[15:0] WRX, WRXL, WRHX WRX, WRLX, WRHX, AD[15:0] Condition
EACL:ACE=0 EACL:ACE=1 EACL:ACE=0 EACL:ACE=1
Symbol
Value Min 3tCYC/2 - 15 5tCYC/2 - 15 tCYC - 15 2tCYC - 15 tCYC - 5 tCYC - 20 Max
Unit
Remarks
tAVWL Valid address WRX time tADVWL
ns ns ns
w/o cycle extension w/o cycle extension
WRX pulse width Valid data output WRX time
tWLWH

tDVWH
ns
FME-MB96350 rev 7
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MB96350 Series
(TA = -40 C to +125 C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter WRX Data hold time WRX Address valid time Symbol Pin WRX, WRLX, WRHX, AD[15:0] WRX, WRLX, WRHX, A[23:16] WRX, WRLX, WRHX, ALE WRX, WRLX, WRHX, ECLK WRX, WRLX, WRHX, CSn WRX, WRLX, WRHX, CSn Condition Value Min tCYC/2 - 15 Max Unit
Remarks
tWHDX

EBM:ACE=1 and EACL:STS=1 other EBM:ACE and EACL:STS setting EACL:ACE=0
ns
tWHAX
tCYC/2 - 15 2tCYC - 10 tCYC - 10 tCYC/2 - 10 tCYC/2 - 15
3tCYC/2 - 15 5tCYC/2 - 15
ns
WRX ALE time
tWHLH
ns
WRX ECLK time CSn WRX time
tWLCH
ns
tCSLWL
ns
EACL:ACE=1
WRX CSn time
tWHCSH
ns
(TA = -40 C to +125 C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin WRX, WRLX, WRHX, A[23:16] WRX, WRLX, WRHX, AD[15:0] WRX, WRXL, WRHX WRX, WRLX, WRHX, AD[15:0] WRX, WRLX, WRHX, AD[15:0] WRX, WRLX, WRHX, A[23:16] Condition
EACL:ACE=0 EACL:ACE=1 EACL:ACE=0 EACL:ACE=1
Value Min 3tCYC/2 - 20 5tCYC/2 - 20 tCYC - 20 2tCYC - 20 tCYC - 8 tCYC - 25 Max
Unit
Remarks
tAVWL Valid address WRX time tADVWL
ns ns ns
w/o cycle extension w/o cycle extension
WRX pulse width Valid data output WRX time WRX Data hold time WRX Address valid time
tWLWH

tDVWH
ns
tWHDX

tCYC/2 - 20
ns
tWHAX
tCYC/2 - 20
ns
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FME-MB96350 rev 7
MB96350 Series
(TA = -40 C to +125 C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Symbol Pin Condition
EBM:ACE=1 and EACL:STS=1 other EBM:ACE and EACL:STS setting EACL:ACE=0
Value Min 2tCYC - 15 tCYC - 15 tCYC/2 - 15 tCYC/2 - 20 Max 3tCYC/2 - 20 5tCYC/2 - 20
Unit
Remarks
WRX ALE time
tWHLH
WRX, WRLX, WRHX, ALE WRX, WRLX, WRHX, ECLK WRX, WRLX, WRHX, CSn WRX, WRLX, WRHX, CSn
ns
WRX ECLK time CSn WRX time
tWLCH
ns
tCSLWL
ns
EACL:ACE=1
WRX CSn time
tWHCSH
ns
tWLCH 0.8*VCC ECLK
tWHLH ALE tAVWL tADVWL WRX (WRLX, WRHX) tWLWH .
0.2*VCC
tCSLWL CSn
tWHCSH
tWHAX A[23:16] tDVWH AD[15:0]
tWHDX
Address
Write data
Refer to the Hardware Manual for detailed Timing Charts
FME-MB96350 rev 7
79
MB96350 Series
Ready Input Timing
Parameter RDY setup time RDY hold time (TA = -40 C to +125 C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Pin RDY RDY Test Condition Rated Value Min 35 0 Max Units ns ns Remarks
Symbol tRYHS tRYHH
(TA = -40 C to +125 C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter RDY setup time RDY hold time Symbol tRYHS tRYHH Pin RDY RDY Test Condition Rated Value Min 45 0 Max Units ns ns Remarks
Note : If the RDY setup time is insufficient, use the auto-ready function.
ECLK
0.8*VCC
tRYHS RDY When WAIT is not used. VIH
tRYHH VIH
RDY When WAIT is used.
VIL
Refer to the Hardware Manual for detailed Timing Charts
Hold Timing
Parameter Pin floating HAKX time
(TA = -40 C to +125 C, VCC = 5.0 V 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Symbol tXHAL tHAHV Pin HAKX HAKX Condition Value Min Max tCYC - 20 tCYC + 20 tCYC - 20 tCYC + 20 Units ns ns Remarks
HAKX time Pin valid time
(TA = -40 C to +125 C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF) Parameter Pin floating HAKX time HAKX time Pin valid time Symbol tXHAL tHAHV Pin HAKX HAKX Condition Value Min Max tCYC - 25 tCYC + 25 tCYC - 25 tCYC + 25 Units ns ns Remarks
80
FME-MB96350 rev 7
MB96350 Series
HAKX 0.2*VCC tXHAL Each pin 0.8*VCC 0.2*VCC High-Z
0.8*VCC
tHAHV
Refer to the Hardware Manual for detailed Timing Charts
FME-MB96350 rev 7
81
MB96350 Series
USART timing
WARNING: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output timing described in the different tables must then be increased by 10ns. (TA = -40C to 125C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF) VCC = AVCC= 4.5V VCC = AVCC= 3.0V to 5.5V to 4.5V Unit Min Max Min Max 4 tCLKP1 -20 Internal Shift Clock Mode N*tCLKP1 - 20 *1 tCLKP1 + 45 0 tCLKP1 + 10 tCLKP1 + 10 External Shift Clock Mode tCLKP1/2 + 10 tCLKP1 + 10 +20 2 tCLKP1 + 45 20 20 4 tCLKP1 -30 N*tCLKP1 30 *1 tCLKP1 + 55 0 tCLKP1 + 10 tCLKP1 + 10 tCLKP1/2 + 10 tCLKP1 + 10 +30 2 tCLKP1 + 55 20 20 ns ns ns ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time SOT SCK delay time Valid SIN SCK SCK Valid SIN hold time Serial clock "L" pulse width Serial clock "H" pulse width SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time SCK fall time SCK rise time
Symbol tSCYCI tSLOVI tOVSHI tIVSHI tSHIXI tSLSHE tSHSLE tSLOVE tIVSHE tSHIXE tFE tRE
Pin SCKn SCKn, SOTn SCKn, SOTn SCKn, SINn SCKn, SINn SCKn SCKn SCKn, SOTn SCKn, SINn SCKn, SINn SCKn SCKn
Condition
Notes: * AC characteristic in CLK synchronized mode. * CL is the load capacity value of pins when testing. * Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. These parameters are shown in "MB96300 Super series HARDWARE MANUAL" * tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns *1: Parameter N depends on tSCYCI and can be calculated as follows: * if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2 * if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1 Examples: tSCYCI N 4*tCLKP1 5*tCLKP1, 6*tCLKP1 7*tCLKP1, 8*tCLKP1 ... 82 2 3 4 ... FME-MB96350 rev 7
MB96350 Series
tSCYCI SCK for ESCR:SCES = 0 0.8*VCC 0.2*VCC 0.2*VCC
SCK for ESCR:SCES = 1
0.8*VCC 0.2*VCC tSLOVI tOVSHI 0.8*VCC 0.2*VCC tIVSHI VIH VIL tSHIXI VIH VIL
0.8*VCC
SOT
SIN
Internal Shift Clock Mode
tSLSHE SCK for ESCR:SCES = 0 VIH VIL VIL VIH
tSHSLE VIH
SCK for ESCR:SCES = 1 tFE
VIH VIL tSLOVE
VIH VIL tRE VIL
SOT
0.8*VCC 0.2*VCC tIVSHE VIH VIL tSHIXE VIH VIL
SIN
External Shift Clock Mode
FME-MB96350 rev 7
83
MB96350 Series
I2C Timing
(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V,VSS = AVSS =0V) Parameter SCL clock frequency Hold time (repeated) START condition SDASCL "L" width of the SCL clock "H" width of the SCL clock Set-up time for a repeated START condition SCLSDA Data hold time SCLSDA Data set-up time SDASCL Set-up time for STOP condition SCLSDA Bus free time between a STOP and START condition Output fall time from 0.7*Vcc to 0.3*Vcc with a bus capacitance from 10 pF to 400 pF Capacitive load for each bus line Pulse width of spikes which will be suppressed by input noise filter Symbol fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tBUS tof Cb tSP Standard-mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 20 + 0.1*Cb *2 n/a Max 100 3.45 250 400 n/a Fast-mode*1 Min 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 20 + 0.1*Cb *2 0 Max 400 0.9 250 400 1*tCLKP1*3 Unit kHz s s s s s ns s s ns pF ns
*1 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz. *2 : Cb = capacitance of one bus line in pF. *3 : tCLKP1 is the cycle time of the periperal clock CLKP1.
SDA tBUS
tLOW SCL
tSUDAT
tHDSTA
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
* VOH = 0.7 * VCC * VOL = 0.3 * VCC * CMOS Hysteresis 0.7/0.3 input selected
84
FME-MB96350 rev 7
MB96350 Series
5. Analog Digital Converter
(TA = -40 C to +125 C, 3.0 V AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero transition voltage Full scale transition voltage Compare time Sampling time Symbol VOT VFST Pin ANn ANn Value Min Typ Max 10 3 2.5 1.9 Unit bit LSB LSB LSB V V s s s s 4.5V VCC 5.5V 3.0V VCC < 4.5V 4.5V VCC 5.5V 3.0V VCC < 4.5V Remarks
AVRL - AVRL+ AVRL + 1.5 LSB 0.5 LSB 2.5 LSB AVRH - AVRH - AVRH + 3.5 LSB 1.5 LSB 0.5 LSB 1.0 2.0 0.5 1.2 -1 16,500 +1
Analog input leakage current (during conversion)
IAIN
ANn -1.2 2.5 0.7 +1.2 AVRH AVcc 0.25 AVCC 5 5 1 5 4
TA 105 C, A AVSS, AVRL < VI < AVCC, AVRH 105 C < TA 125 C, A AVSS, AVRL < VI < AVCC, AVRH V V V mA A/D Converter active A A/D Converter not operated
Analog input voltage range Reference voltage range
VAIN AVRH AVRL IA
ANn AVRH AVRL AVcc AVcc AVRH/ AVRL AVRH/ AVRL ANn
AVRL 0.75 AVcc AVSS -
Power supply current
IAH IR IRH -
Reference voltage current Offset between input channels
mA A/D Converter active A LSB A/D Converter not operated
Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller.
FME-MB96350 rev 7
85
MB96350 Series
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter. Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition error and nonlinearity error. Nonlinearity error: Deviation between a line across zero-transition line ("00 0000 0000" <--> "00 0000 0001") and full-scale transition line ("11 1111 1110" <--> "11 1111 1111") and actual conversion characteristics. Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. Zero reading voltage: Input voltage which results in the minimum conversion value. Full scale reading voltage: Input voltage which results in the maximum conversion value. Total error
3FF 3FE 3FD Digital output {1 LSB x (N - 1) + 0.5 LSB} Actual conversion characteristics 1.5 LSB
004 003 002 001 0.5 LSB AVRL Analog input
VNT (Actually-measured value) Actual conversion characteristics Ideal characteristics
AVRH
Total error of digital output "N" =
VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB AVRH - AVRL 1 LSB = (Ideal value) [V] 1024
[LSB]
N: A/D converter digital output value VOT (Ideal value) = AVRL + 0.5 LSB [V] VFST (Ideal value) = AVRH - 1.5 LSB [V] VNT : A voltage at which digital output transitions from (N - 1) to N.
86
FME-MB96350 rev 7
MB96350 Series
Nonlinearity error
3FF 3FE 3FD Digital output Actual conversion characteristics {1 LSB x (N - 1) + VOT } N+1 VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics
Differential nonlinearity error
Ideal characteristics Actual conversion characteristics
Digital output
N
004 003 002
N-1
V (N + 1) T (actual measurement value) VNT (actual measurement value) Actual conversion characteristics AVRH Analog input
Ideal characteristics 001 VOT (actual measurement value) AVRL Analog input AVRH
N-2
AVRL
Nonlinearity error of digital output N = Differential nonlinearity error of digital output N = 1 LSB =
VNT - {1 LSB x (N - 1) + VOT} 1 LSB V (N+1) T - VNT 1 LSB VFST - VOT 1022 -1 LSB [LSB] [V]
[LSB]
N : A/D converter digital output value VOT : Voltage at which digital output transits from "000H" to "001H." VFST : Voltage at which digital output transits from "3FEH" to "3FFH."
FME-MB96350 rev 7
87
MB96350 Series
Accuracy and setting of the A/D Converter sampling time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision. To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and the AVcc voltage level. The following replacement model can be used for the calculation:
MCU
Analog input Rext Source Cext CIN CADC RADC
Comparator
Sampling switch
Rext: external driving impedance Cext: capacitance of PCB at A/D converter input CIN: capacitance of MCU input pin: 15pF (max) RADC: resistance within MCU: 2.6k (max) for 4.5V AVcc 5.5V 12k (max) for 3.0V AVcc < 4.5V CADC: sampling capacitance within MCU: 10pF (max)
The sampling time should be set to minimum "7". The following approximation formula for the replacement model above can be used: Tsamp [min] = 7 x (Rext x (Cext + CIN) + (Rext + RADC) x CADC) * Do not select a sampling time below the absolute minimum permitted value (0.5s for 4.5V AVcc 5.5V; 1.2 s for 3.0V AVcc < 4.5V). * If the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. In this case the internal sampling capacitance CADC will be charged out of this external capacitance. * A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL cannot be compensated by an external capacitor. * The accuracy gets worse as |AVRH - AVRL| becomes smaller.
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FME-MB96350 rev 7
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6. Low Voltage Detector characteristics
(TA = -40 C to +125 C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V) Parameter Stabilization time Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 Level 9 Level 10 Level 11 Level 12 Level 13 Level 14 Level 15 Symbol TLVDSTAB VDL0 VDL1 VDL2 VDL3 VDL4 VDL5 VDL6 VDL7 VDL8 VDL9 VDL10 VDL11 VDL12 VDL13 VDL14 VDL15 Value *1 Min 2.7 2.9 3.1 3.5 3.6 3.7 3.8 3.9 4.0 4.1 Max 75 2.9 3.1 3.3 3.75 3.85 3.95 4.05 4.15 4.25 4.35 Value *2 Min 2.5 2.8 3 3.35 3.5 3.6 3.7 3.8 3.9 3.95 Max 110 2.9 3.2 3.4 3.8 3.95 4.1 4.2 4.3 4.4 4.5 Unit s V V V V V V V V V V Remarks After power-up or change of detection level
CILCR:LVL[3:0]="0000" CILCR:LVL[3:0]="0001" CILCR:LVL[3:0]="0010" CILCR:LVL[3:0]="0011" CILCR:LVL[3:0]="0100" CILCR:LVL[3:0]="0101" CILCR:LVL[3:0]="0110" CILCR:LVL[3:0]="0111" CILCR:LVL[3:0]="1000" CILCR:LVL[3:0]="1001"
not used not used not used not used not used not used
not used not used 2.6 3 V
CILCR:LVL[3:0]="1100"
not used not used not used
*1: valid for all devices except devices listed under "*2" *2: valid for: MB96F353/F355 CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register.
V For correct detection, the slope of the voltage level must satisfy dV 0.004 ----- .
Faster variations are regarded as noise and may not be detected.
dt
s
The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of "Level 0" (VDL0_MIN). The electrical characteristics however are only valid in the specified range (usually down to 3.0V).
FME-MB96350 rev 7
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MB96350 Series
Low Voltage Detector Operation
In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the reset and startup behavior, please refer to the corresponding hardware manual chapter.
Voltage [V] VCC VDLx, Max VDLx, Min dV dt Time [s] Normal Operation Low Voltage Reset Assertion Power Reset Extension Time
90
FME-MB96350 rev 7
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7. FLASH memory program/erase characteristics
(TA = -40C to 105C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V) Parameter Sector erase time Chip erase time Word (16-bit width) programming time Program/Erase cycle Flash data retention time Value Min 10 000 20 Typ 0.9 n*0.9 23 Max 3.6 n*3.6 370 Unit s s us cycle year *1 Remarks Without erasure pre-programming time Without erasure pre-programming time (n is the number of Flash sector of the device) Without overhead time for submitting write command
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius equation to convert high temperature measurements into normalized value at 85oC)
FME-MB96350 rev 7
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MB96350 Series
EXAMPLE CHARACTERISTICS
1. Temperature dependency of power supply currents
The following diagrams show the current consumption of samples with typical wafer process parameters in different operation modes. Common condition for all operation modes: * VCC = AVCC = 5.0V * Main clock = 4MHz external clock * Sub clock = 32kHz external clock Operation mode details: Mode name PLL Run 56 Details PLL Run mode current ICCPLL with the following settings: * fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = 56MHz * fCLKP2 = 28MHz * Regulator in High Power Mode * Core voltage at 1.9V (VRCR:HPM[1:0] = 11B) * 2 Flash/ROM wait states (MTCRA=233AH) * RC oscillator and Sub oscillator stopped PLL Run mode current ICCPLL with the following settings: * fCLKS1 = fCLKS2 = 96MHz * fCLKB = fCLKP1 = 48MHz * fCLKP2 = 24MHz * Regulator in High Power Mode * Core voltage at 1.9V (VRCR:HPM[1:0] = 11B) * 1 Flash/ROM wait states (MTCRA=6B09H) * RC oscillator and Sub oscillator stopped PLL Run mode current ICCPLL with the following settings: * fCLKS1 = fCLKS2 = 48MHz * fCLKB = fCLKP1 = fCLKP2 = 24MHz * Regulator in High Power Mode * Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) * 0 Flash/ROM wait states (MTCRA=2208H) * RC oscillator and Sub oscillator stopped Main Run mode current ICCMAIN with the following settings: * fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 4MHz * Regulator in High Power Mode * Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) * 1 Flash/ROM wait states (MTCRA=0239H) * PLL, RC oscillator and Sub oscillator stopped
PLL Run 48
PLL Run 24
Main Run
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Mode name RC Run 2M Details RC Run mode current ICCRCH with the following settings: * RC oscillator set to 2MHz (CKFCR:RCFS = 1) * fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 2MHz * Regulator in High Power Mode * Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) * 1 Flash/ROM wait states (MTCRA=0239H) * PLL, Main oscillator and Sub oscillator stopped RC Run mode current ICCRCL with the following settings: * RC oscillator set to 100kHz (CKFCR:RCFS = 0) * fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 100kHz * Regulator in Low Power Mode A (SMCR:LPMS = 1) * Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) * 1 Flash/ROM wait states (MTCRA=0239H) * PLL, Main oscillator and Sub oscillator stopped Sub Run mode current ICCSUB with the following settings: * fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 32kHz * Regulator in Low Power Mode A (by hardware) * Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) * 1 Flash/ROM wait states (MTCRA=0239H) * PLL, RC oscillator and Main oscillator stopped PLL Sleep mode current ICCSPLL with the following settings: * fCLKS1 = fCLKS2 = fCLKP1 = 56MHz * fCLKP2 = 28MHz * Regulator in High Power Mode * Core voltage at 1.9V (VRCR:HPM[1:0] = 11B) * RC oscillator and Sub oscillator stopped PLL Sleep mode current ICCSPLL with the following settings: * fCLKS1 = fCLKS2 = 96MHz * fCLKP1 = 48MHz * fCLKP2 = 24MHz * Regulator in High Power Mode * Core voltage at 1.9V (VRCR:HPM[1:0] = 11B) * RC oscillator and Sub oscillator stopped PLL Sleep mode current ICCSPLL with the following settings: * fCLKS1 = fCLKS2 = 48MHz * fCLKP1 = fCLKP2 = 24MHz * Regulator in High Power Mode * Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) * RC oscillator and Sub oscillator stopped Main Sleep mode current ICCSMAIN with the following settings: * fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 4MHz * Regulator in High Power Mode * Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) * PLL, RC oscillator and Sub oscillator stopped
RC Run 100k
Sub Run
PLL Sleep 56
PLL Sleep 48
PLL Sleep 24
Main Sleep
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Mode name RC Sleep 2M Details RC Sleep mode current ICCSRCH with the following settings: * RC oscillator set to 2MHz (CKFCR:RCFS = 1) * fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 2MHz * Regulator in High Power Mode * Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) * PLL, Main oscillator and Sub oscillator stopped RC Sleep mode current ICCSRCL with the following settings: * RC oscillator set to 100kHz (CKFCR:RCFS = 0) * fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 100kHz * Regulator in Low Power Mode A (SMCR:LPMSS = 1) * Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) * PLL, Main oscillator and Sub oscillator stopped Sub Sleep mode current ICCSSUB with the following settings: * fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 32kHz * Regulator in Low Power Mode A (by hardware) * Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) * PLL, RC oscillator and Main oscillator stopped PLL Timer mode current ICCTPLL with the following settings: * fCLKS1 = fCLKS2 = 48MHz * Regulator in High Power Mode * Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) * RC oscillator and Sub oscillator stopped Main Timer mode current ICCTMAIN with the following settings: * fCLKS1 = fCLKS2 = 4MHz * Regulator in Low Power Mode A (SMCR:LPMSS = 1) * Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) * PLL, RC oscillator and Sub oscillator stopped RC Timer mode current ICCTRCH with the following settings: * RC oscillator set to 2MHz (CKFCR:RCFS = 1) * fCLKS1 = fCLKS2 = 2MHz * Regulator in Low Power Mode A (SMCR:LPMSS = 1) * Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) * PLL, Main oscillator and Sub oscillator stopped RC Timer mode current ICCTRCL with the following settings: * RC oscillator set to 100kHz (CKFCR:RCFS = 0) * fCLKS1 = fCLKS2 = 100kHz * Regulator in Low Power Mode A (SMCR:LPMSS = 1) * Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) * PLL, Main oscillator and Sub oscillator stopped Sub Timer mode current ICCTSUB with the following settings: * fCLKS1 = fCLKS2 = 32kHz * Regulator in Low Power Mode A (by hardware) * Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B) * PLL, RC oscillator and Main oscillator stopped
RC Sleep 100k
Sub Sleep
PLL Timer 48
Main Timer
RC Timer 2M
RC Timer 100k
Sub Timer
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Mode name Stop 1.8V Details Stop mode current ICCH with the following settings: * Regulator in Low Power Mode B (by hardware) * Core voltage at 1.8V (VRCR:LPMB[2:0] = 110B) Stop mode current ICCH with the following settings: * Regulator in Low Power Mode B (by hardware) * Core voltage at 1.2V (VRCR:LPMB[2:0] = 000B) MB96F353/F355 PLL Run and Sleep mode currents
50
Stop 1.2V
PLL Run 48
40
PLL Run 56
30
Icc[mA]
20 10 0 -60
PLL Run 24
PLL Sleep 48 PLL Sleep 56
PLL Sleep 24
-40
-20
0
20
40
60
80
100
120
Ta [C]
FME-MB96350 rev 7
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MB96350 Series
MB96F353/F355 operation modes with medium currents
5
4
Main Run
3
Icc[mA]
RC Run 2M
2
PLL Timer 48
1
Main Sleep RC Sleep 2M
0 -60 -40 -20 0 20 40 60 80 100 120
Ta [C]
MB96F353/F355 Low power mode currents
1
RC Run 100k
0.1
Sub Run Main Timer RC Timer 2M
Icc[mA]
RC Sleep 100k Sub Sleep Sub Timer RC Timer 100k
0.01
Stop 1.8V Stop 1.2V
0.001 -60 -40 -20 0 20 40 60 80 100 120
Ta [C]
96
FME-MB96350 rev 7
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MB96F356 PLL Run and Sleep mode currents
50
PLL Run 48
40
PLL Run 56
30
Icc[mA]
20 10 0 -60
PLL Run 24
PLL Sleep 48 PLL Sleep 56 PLL Sleep 24
-40
-20
0
20
40
60
80
100
120
Ta [C]
MB96F356 operation modes with medium currents
5
4
Main Run
3
Icc[mA]
RC Run 2M
2
PLL Timer 48 Main Sleep RC Sleep 2M
1
0 -60 -40 -20 0 20 40 60 80 100 120
Ta [C]
FME-MB96350 rev 7
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MB96350 Series
MB96F356 Low power mode currents
1
0.1
RC Run 100k Sub Run Main Timer RC Timer 2M
Icc[mA]
Sub Sleep RC Sleep 100k Sub Timer RC Timer 100k
0.01
Stop 1.8V Stop 1.2V
0.001 -60 -40 -20 0 20 40 60 80 100 120
Ta [C]
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FME-MB96350 rev 7
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2. Frequency dependency of power supply currents in PLL Run mode
The following diagrams show the current consumption of samples with typical wafer process parameters in PLL Run mode at different frequencies and Flash timing settings. Measurement conditions: * VCC = AVCC = 5.0V * Ta = 25C * fCLKS1 = fCLKB or fCLKS1 = 2*fCLKB as described in diagram * fCLKS2 = fCLKS1 * fCLKP1 = fCLKB * fCLKP2 = fCLKB/2 * Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) or 1.9V (VRCR:HPM[1:0] = 11B) as described in diagram * Main clock = 4MHz external clock * Flash memory timing settings: * MTCRA=2128H/2208H (0 Flash wait states, fCLKS1 = 2*fCLKB) * MTCRA=0239H/2129H (1 Flash wait state, fCLKS1 = fCLKB) * MTCRA=4C09H/6B09H (1 Flash wait state, fCLKS1 = 2*fCLKB) * MTCRA=233AH (2 Flash wait states, fCLKS1 = fCLKB) * Average Flash access rate (number of read accesses to the Flash per CLKB clock cycle, no buffer hit): * 0 Flash wait states: 0.5 * 1 Flash wait states: 0.33 * 2 Flash wait states: 0.25 MB96F353/F355 PLL Run mode currents
45
1 Flash wait state (CLKS1=2*CLKB, 1.9V)
40
35
1 Flash wait state (CLKS1=2*CLKB, 1.8V)
30
2 Flash wait states (CLKS1=CLKB, 1.9V)
ICCPLL (mA)
25
0 Flash wait states (CLKS1=2*CLKB, 1.8V) 2 Flash wait states (CLKS1=CLKB, 1.8V)
20
15
1 Flash wait state (CLKS1=CLKB, 1.8V)
10
: Specified in "DC characteristics"
5
0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 CLKB/CLKP1 (MHz)
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MB96350 Series
MB96F356 PLL Run mode currents
45
1 Flash wait state (CLKS1=2*CLKB, 1.9V)
40
35
1 Flash wait state (CLKS1=2*CLKB, 1.8V)
30
2 Flash wait states (CLKS1=CLKB, 1.9V)
ICCPLL (mA)
25
0 Flash wait states (CLKS1=2*CLKB, 1.8V) 2 Flash wait states (CLKS1=CLKB, 1.8V)
20
15
1 Flash wait state (CLKS1=CLKB, 1.8V)
10
: Specified in "DC characteristics"
5
0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 CLKB/CLKP1 (MHz)
100
FME-MB96350 rev 7
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PACKAGE DIMENSION MB96(F)35x LQFP 64 - M23
64-pin plastic LQFP
Lead pitch Package width x package length Lead shape Sealing method Mounting height Code (Reference)
0.65 mm 12.0 x 12.0 mm Gullwing Plastic mold 1.70 mm MAX P-LFQFP64-12x12-0.65
(FPT-64P-M23)
64-pin plastic LQFP (FPT-64P-M23)
14.000.20(.551.008)SQ *12.000.10(.472.004)SQ
48 33
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
0.1450.055 (.0057.0022)
49
32
0.10(.004) Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0.25(.010) INDEX 0~8
64 17
1
16
"A"
0.65(.026)
0.320.05 (.013.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.13(.005)
M
(c)2003-2008 FUJITSU MICROELECTRONICS LIMITED F64034S-c-1-2 C 2003 FUJITSU LIMITED F64034S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/
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PACKAGE DIMENSION MB96(F)35x LQFP 64 - M24
64-pin plastic LQFP
Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight
0.50 mm 10.0 x 10.0 mm Gullwing Plastic mold 1.70 mm MAX 0.32 g P-LFQFP64-10x10-0.50
(FPT-64P-M24)
Code (Reference)
64-pin plastic LQFP (FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
12.000.20(.472.008)SQ
* 10.000.10(.394.004)SQ
48 33
0.1450.055 (.006.002)
49
32
Details of "A" part 0.08(.003) 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX
64 17
0~8 "A" 0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.25(.010)
LEAD No.
1
16
0.50(.020)
0.200.05 (.008.002)
0.08(.003)
M
(c)2005-2008 FUJITSU MICROELECTRONICS LIMITED F64036S-c-1-2 C
2005 FUJITSU LIMITED F64036S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/
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ORDERING INFORMATION
MCU with CAN controller
Part number MB96F353RSB PMC-GSE2 MB96F353RWB PMC-GSE2 MB96F353RSB PMC1-GSE2 MB96F353RWB PMC1-GSE2 MB96F355RSB PMC-GSE2 MB96F355RWB PMC-GSE2 MB96F355RSB PMC1-GSE2 MB96F355RWB PMC1-GSE2 MB96F356YSB PMC-GSE2 MB96F356RSB PMC-GSE2 MB96F356YWB PMC-GSE2 MB96F356RWB PMC-GSE2 MB96F356YSB PMC1-GSE2 MB96F356RSB PMC1-GSE2 MB96F356YWB PMC1-GSE2 MB96F356RWB PMC1-GSE2 MB96V300BRB-ES (for evaluation) Emulated by ext. RAM Flash A (288KB) No Yes Yes Flash A (160KB) Flash A (96KB) Flash/ROM Subclock No Yes No Yes No Yes No Yes No Yes Yes No Yes No Yes No Yes No No 416 pin Plastic BGA (BGA-416P-M02) 64 pins Plastic LQFP (FPT-64P-M24) 64 pins Plastic LQFP (FPT-64P-M23) No 64 pins Plastic LQFP (FPT-64P-M23) 64 pins Plastic LQFP (FPT-64P-M24) Persistent Low Voltage Reset Package 64 pins Plastic LQFP (FPT-64P-M23) 64 pins Plastic LQFP (FPT-64P-M24)
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MB96350 Series
MCU without CAN controller
Part number MB96F353ASB PMC-GSE2 MB96F353AWB PMC-GSE2 MB96F353ASB PMC1-GSE2 MB96F353AWB PMC1-GSE2 MB96F355ASB PMC-GSE2 MB96F355AWB PMC-GSE2 MB96F355ASB PMC1-GSE2 MB96F355AWB PMC1-GSE2 MB96F356ASB PMC-GSE2 MB96F356AWB PMC-GSE2 MB96F356ASB PMC1-GSE2 MB96F356AWB PMC1-GSE2 Flash A (288KB) Flash A (160KB) Flash A (96KB) Flash/ROM Subclock No Yes No Yes No Yes No Yes No Yes No Yes No 64 pins Plastic LQFP (FPT-64P-M24) 64 pins Plastic LQFP (FPT-64P-M23) 64 pins Plastic LQFP (FPT-64P-M24) Persistent Low Voltage Reset Package 64 pins Plastic LQFP (FPT-64P-M23) 64 pins Plastic LQFP (FPT-64P-M24) 64 pins Plastic LQFP (FPT-64P-M23)
This datasheet is also valid for the following outdated devices:
MB96F356YSA, MB96F356RSA, MB96F356YWA, MB96F356RWA, MB96F356ASA, MB96F356AWA, MB96F353RSA, MB96F353RWA, MB96F355RSA, MB96F355RWA, MB96F353ASA, MB96F353AWA, MB96F355ASA, MB96F355AWA.
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REVISION HISTORY
Revision Prelim 1 Prelim 2 Prelim 3
Date 2007-05-03 2007-05-25 2007-11-27 Creation Electrical characteristics update
Modification
Package description is removed from cover page. Typos corrections in product lineup. Product option details added Electrical characteristics update Update of the block diagram Update of the IO map Pin circuit type, LVD characteristics and example characteristics chapters added Update of the block diagram: external bus address lines, clock output function pins, AVRL removed from ADC block, relayout. RAMSTART value is corrected IO map regenerated Memory map and Flash configuration reworked Few typos corrected accross the document. Flash bank renaming. Ordering information: package type corrected. IO circuit drawings modified. * * * * * * * * Reload Timer RLT 6 for PPGs added Block diagram corrected: ICU2 deleted, TTG2,3 deleted, TTG8,9 added Pin function description corrected with all existing pin types I/O circuit type diagrams corrected Memory map cleaned up "Flash sector configuration" replaced by corrected "User ROM Memory map for Flash devices" Parallel Flash programming spec removed IO map table regenerated: - Port register: Naming style corrected - Memory control registers renamed (Main -> A) - addresses after 000BFFh removed Handling devices: AD converter items added Absolute maximum ratings: Pd and Ta specified more precisely Run and Sleep mode currents: more conditions added (1WS settings) Run mode current spec in 48/24MHz mode corrected Maximum CLKS1 frequency corrected at 1.8V External bus timings: missing conditions added and readability improved Ordering information updated Typos and formatting corrected
Prelim 4
2007-12-20
Prelim 5
2008-02-04
* * * * * * * *
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Revision 6 Date 2009-01-09 Modification * Format adjusted to official Fujitsu Microelectronics datasheet standard (mainly style changes and official notes and disclaimer added) * Numbering of Electrical Characteristics subchapters automated * CANless devices added (MB96F356A) * I/O map: Added node about reserved registers * Serial programming interface: Note about handshaking pins improved * specified AD converter channel offset to 4LSB * package code of MB96V300 corrected in ordering information * Added voltage condition to pull-up resistance spec * Ordering information: column "Flash/ROM" added, column "Remarks" removed * Official package dimension drawing with additional notes added * Empty pages removed * Handling devices: Notes added about Serial communication and about using ceramic resonators. * Feature list and AC Characteristics: 16MHz maximum frequency is valid for crystal oscillators. For resonators, maximum frequency depends on Q-factor * AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz * VOL3 spec improved: spec valid for 3mA load for full Vcc range * MB96F353/F355 added (under development) * Free running timer (I/O Timer) 2 and 3 added (without clock input pin) * Input capture ICU9 and ICU10 added (without input pin, only for LIN USART) * C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted * "Preliminary" watermark removed
106
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Revision 7 Date 2010-06-24 Modification * AD converter IAIN spec improved: 1uA valid up to 105deg, 1.2uA above 105deg * Low voltage detector: Detection levels of MB96F353/F355 updated * Note added that PLL phase jitter spec does not include jitter coming from Main clock * Note added in DC characteristics how to select driving strength of ports * I2C AC spec updated: tof, Cb and tSP spec added, wrong footnotes and Condition removed * I/O Circuit type: Note added for type "N" (slew rate control according to I2C spec) * Example characteristics updated, new figures added showing dependency of PLL Run mode current on frequency * Updated Power Supply current spec in Run/Sleep/Timer/Stop modes (new spec items in PLL Run/Sleep mode, small adjustment of most other values) * Package dimension: Added the following sentence under the figure: "Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/" * AD converter: Impact of input pin capacitance and external capacitance added to formula for calculation of the sampling time * Added specification of RC clock stabilization time * Ordering information updated: MB96F353/F355**A -> MB96F353/F355**B, the device development is finished * Feature description I2C: `8-bit addressing' corrected to `7-bit addressing' * Feature description PPG: `Reload timer overflow as clock input' corrected to `Reload timer underflow as clock input' * ICCLVD specification updated, at 125deg typical value is 7uA and maximum value is 20uA * Company name updated on the cover page: Fujitsu Microelectronics Limited -> Fujitsu Semiconductor Limited
FME-MB96350 rev 7
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MB96350 Series
FME-MB96350 rev 7
MB96350 Series
FME-MB96350 rev 7
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MB96350 Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department
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FME-MB96350 rev 7

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